STM8AF6246TCSSSY STMicroelectronics, STM8AF6246TCSSSY Datasheet - Page 22
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STM8AF6246TCSSSY
Manufacturer Part Number
STM8AF6246TCSSSY
Description
8 BITS MICROCONTR
Manufacturer
STMicroelectronics
Series
STM8Ar
Datasheet
1.STM8AF5289TCY.pdf
(106 pages)
Specifications of STM8AF6246TCSSSY
Core Processor
STM8A
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM8AF6246TCSSSY
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STM8AF6246TCSSSY
Manufacturer:
ST
Quantity:
20 000
Product overview
5.8
5.9
5.9.1
22/106
Analog to digital converter (ADC)
The STM8A products described in this datasheet contain a 10-bit successive approximation
ADC with up to 16 multiplexed input channels, depending on the package.
The ADC name differs between the datasheet and the STM8A/S reference manual (see
Table
Table 9.
ADC features
●
●
●
●
●
●
●
●
●
Communication interfaces
The following sections give a brief overview of the communication peripheral. Some
peripheral names differ between the datasheet and the STM8A/S reference manual (see
Table
Table 10.
Universal synchronous/asynchronous receiver transmitter (USART)
The devices covered by this datasheet contain one USART interface. The USART can
operate in standard SCI mode (serial communication interface, asynchronous) or in SPI
emulation mode. It is equipped with a 16 bit fractional prescaler. It features LIN master
support.
Detailed feature list:
●
●
10-bit resolution
Single and continuous conversion modes
Programmable prescaler: f
Conversion trigger on timer events, and external events
Interrupt generation at end of conversion
Selectable alignment of 10-bit data in 2 x 8 bit result registers
Shadow registers for data consistency
ADC input range: VSSA = VIN = VDDA
Schmitt-trigger on analog inputs can be disabled to reduce power consumption
Full duplex, asynchronous communications
NRZ standard format (mark/space)
9).
10).
Peripheral name in datasheet
Peripheral name in datasheet
ADC naming
Communication peripheral naming correspondence
LINUART
USART
ADC
Doc ID 14395 Rev 8
MASTER
divided by 2 to 18
Peripheral name in reference manual
Peripheral name in reference manual
STM8AF52/62xx, STM8AF51/61xx
(RM0016)
(RM0016)
UART1
UART3
ADC2