PIC18F14K50T-I/SO Microchip Technology, PIC18F14K50T-I/SO Datasheet - Page 87
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PIC18F14K50T-I/SO
Manufacturer Part Number
PIC18F14K50T-I/SO
Description
16 KB Flash, 768 RAM, 15 I/O, 10-Bit ADC, USB 2.0 20 SOIC .300in T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(10 pages)
3.PIC18F13K50-ISS.pdf
(2 pages)
4.PIC18F14K50-ISS.pdf
(4 pages)
Specifications of PIC18F14K50T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
15
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
A/d Bit Size
10 bit
A/d Channels Available
11
Height
2.05 mm
Length
12.8 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7.49 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC244023 - PROC EXTENS PAK PIC18F1XK50DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOIC
Lead Free Status / Rohs Status
Details
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F14K50-ISS PDF datasheet #4
- Current page: 87 of 420
- Download datasheet (4Mb)
TABLE 9-1:
2010 Microchip Technology Inc.
RA0/IOCA0/D+/
PGD
RA1/IOCA1/D-/
PGC
RA3/IOCA3/MCLR/
V
RA4/IOCA4/AN3/
OSC2/CLKOUT
RA5/IOCA5/OSC1/
CLKIN
Legend:
PP
Note 1: RA0 and RA1 do not have corresponding TRISA bits. In Port mode, these pins are input only. USB data direction is
Pin
2: RA3 does not have a corresponding TRISA bit. This pin is always an input regardless of mode.
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
determined by the USB configuration.
PORTA I/O SUMMARY
Function
CLKOUT
IOCA0
IOCA1
IOCA3
IOCA4
IOCA5
MCLR
CLKIN
OSC2
OSC1
PGD
PGC
RA0
RA1
RA3
RA4
AN3
RA5
V
D+
D-
PP
Setting
TRIS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
1
1
x
x
0
1
1
x
x
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
XCVR USB bus differential plus line input (internal transceiver).
XCVR USB bus differential plus line output (internal transceiver).
XCVR USB bus differential minus line input (internal transceiver).
XCVR USB bus differential minus line output (internal transceiver).
Type
ANA
ANA
ANA
ANA
ANA
TTL
TTL
DIG
TTL
TTL
DIG
TTL
DIG
TTL
TTL
DIG
DIG
TTL
TTL
I/O
ST
ST
ST
ST
Preliminary
PORTA<0> data input; disabled when USB enabled.
Interrupt-on-pin change; disabled when USB enabled.
Serial execution data output for ICSP™.
Serial execution data input for ICSP™.
PORTA<1> data input; disabled when USB enabled.
Interrupt-on-pin change; disabled when USB enabled.
Serial execution clock output for ICSP™.
Serial execution clock input for ICSP™.
PORTA<3> data input; enabled when MCLRE Configuration bit is
clear; Programmable weak pull-up.
Interrupt-on-pin change
External Master Clear input; enabled when MCLRE Configuration bit is
set.
High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
LATA<4> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
PORTA<4> data input; Programmable weak pull-up. Enabled in RCIO,
INTIO2 and ECIO modes only.
Interrupt-on-pin change
A/D input channel 3. Default configuration on POR.
Main oscillator feedback output connection (XT, HS and LP modes).
System cycle clock output (F
modes.
LATA<5> data output. Disabled in external oscillator modes.
PORTA<5> data input. Disabled in external oscillator modes; Program-
mable weak pull-up.
Interrupt-on-pin change
Main oscillator input connection.
Main clock input connection.
PIC18F/LF1XK50
OSC
Description
/4) in RC, INTIO1 and EC Oscillator
DS41350E-page 87
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