PIC18F14K50T-I/SO Microchip Technology, PIC18F14K50T-I/SO Datasheet - Page 185
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PIC18F14K50T-I/SO
Manufacturer Part Number
PIC18F14K50T-I/SO
Description
16 KB Flash, 768 RAM, 15 I/O, 10-Bit ADC, USB 2.0 20 SOIC .300in T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(10 pages)
3.PIC18F13K50-ISS.pdf
(2 pages)
4.PIC18F14K50-ISS.pdf
(4 pages)
Specifications of PIC18F14K50T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
15
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
A/d Bit Size
10 bit
A/d Channels Available
11
Height
2.05 mm
Length
12.8 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7.49 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC244023 - PROC EXTENS PAK PIC18F1XK50DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOIC
Lead Free Status / Rohs Status
Details
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F14K50-ISS PDF datasheet #4
- Current page: 185 of 420
- Download datasheet (4Mb)
FIGURE 16-3:
FIGURE 16-4:
TABLE 16-1:
2010 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
(Interrupt Reg. Flag)
Reg. Empty Flag)
Reg. Empty Flag)
Note:
Reg. Empty Flag)
Write to TXREG
(Transmit Buffer
Name
Write to TXREG
(Transmit Shift
(Transmit Shift
BRG Output
(Shift Clock)
BRG Output
(Shift Clock)
RB7/TX/CK
RB7/TX/CK
TRMT bit
TRMT bit
TXIF bit
TXIF bit
This timing diagram shows two consecutive transmissions.
pin
EUSART Transmit Register
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
pin
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
—
—
—
ASYNCHRONOUS TRANSMISSION
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
1 T
Word 1
Transmit Shift Reg
CY
Word 1
Transmit Shift Reg
Word 1
Word 1
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
1 T
CY
Start bit
Start bit
Word 2
DTRXP
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
1 T
CY
bit 0
bit 0
Preliminary
CKTXP
INT0IE
CREN
SYNC
Bit 4
TXIF
TXIE
TXIP
bit 1
Word 1
bit 1
Word 1
ADDEN
SENDB
BRG16
RABIE
SSPIF
SSPIE
SSPIP
Bit 3
PIC18F/LF1XK50
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
—
bit 7/8
bit 7/8
TMR2IF
TMR2IE
TMR2IP
Word 2
Transmit Shift Reg
INT0IF
OERR
TRMT
Stop bit
WUE
Bit 1
Stop bit
Start bit
TMR1IE
TMR1IP
TMR1IF
ABDEN
RABIF
RX9D
TX9D
DS41350E-page 185
Bit 0
Word 2
on page
Values
Reset
bit 0
285
288
288
288
287
287
287
287
287
287
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