PIC18F14K50T-I/SO Microchip Technology, PIC18F14K50T-I/SO Datasheet - Page 292
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PIC18F14K50T-I/SO
Manufacturer Part Number
PIC18F14K50T-I/SO
Description
16 KB Flash, 768 RAM, 15 I/O, 10-Bit ADC, USB 2.0 20 SOIC .300in T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(10 pages)
3.PIC18F13K50-ISS.pdf
(2 pages)
4.PIC18F14K50-ISS.pdf
(4 pages)
Specifications of PIC18F14K50T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
15
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
A/d Bit Size
10 bit
A/d Channels Available
11
Height
2.05 mm
Length
12.8 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7.49 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC244023 - PROC EXTENS PAK PIC18F1XK50DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOIC
Lead Free Status / Rohs Status
Details
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F14K50-ISS PDF datasheet #4
- Current page: 292 of 420
- Download datasheet (4Mb)
PIC18F/LF1XK50
24.1
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh), which
can only be accessed using table reads and table writes.
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
a TBLWT instruction with the TBLPTR pointing to the
Configuration register sets up the address and the data
for the Configuration register write. Setting the WR bit
starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to
to Flash Program
TABLE 24-1:
DS41350E-page 292
300000h CONFIG1L
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
300005h CONFIG3H
300006h CONFIG4L BKBUG
300008h CONFIG5L
300009h CONFIG5H
30000Ah CONFIG6L
30000Bh CONFIG6H
30000Ch CONFIG7L
30000Dh CONFIG7H
3FFFFEh DEVID1
3FFFFFh DEVID2
Legend:
Note 1:
File Name
2:
Configuration Bits
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’
See
BKBUG is only used for the ICD device. Otherwise, this bit is unimplemented and reads as ‘1’.
Register 24-13
(1)
(1)
CONFIGURATION BITS AND DEVICE IDs
Memory”.
MCLRE
DEV10
WRTD
DEV2
IESO
Bit 7
CPD
—
—
—
—
—
—
—
(2)
for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
ENHCPU
Section 4.5 “Writing
FCMEN PCLKEN
EBTRB
WRTB
DEV1
DEV9
Bit 6
CPB
—
—
—
—
—
—
—
USBDIV CPUDIV1 CPUDIV0
WRTC
DEV0
DEV8
Bit 5
—
—
—
—
—
—
—
—
—
Preliminary
WDTPS3
BORV1
PLLEN
REV4
DEV7
Bit 4
—
—
—
—
—
—
—
—
WDTPS2
HFOFST
BORV0
FOSC3
BBSIZ
REV3
DEV6
Bit 3
—
—
—
—
—
—
WDTPS1 WDTPS0
BOREN1 BOREN0 PWRTEN
FOSC2
REV2
DEV5
Bit 2
LVP
—
—
—
—
—
—
—
—
FOSC1
EBTR1
WRT1
REV1
DEV4
Bit 1
CP1
—
—
—
—
—
—
2010 Microchip Technology Inc.
STVREN
WDTEN
FOSC0
EBTR0
WRT0
REV0
DEV3
Bit 0
CP0
—
—
—
—
—
Unprogrammed
--00 0---
0010 0111
---1 1111
---1 1111
1--- 1---
-0-- 01-1
---- --11
11-- ----
---- --11
111- ----
---- --11
-1-- ----
qqqq qqqq
0000 1100
Default/
Value
(1)
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