PIC18F14K50T-I/SO Microchip Technology, PIC18F14K50T-I/SO Datasheet - Page 170
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PIC18F14K50T-I/SO
Manufacturer Part Number
PIC18F14K50T-I/SO
Description
16 KB Flash, 768 RAM, 15 I/O, 10-Bit ADC, USB 2.0 20 SOIC .300in T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(10 pages)
3.PIC18F13K50-ISS.pdf
(2 pages)
4.PIC18F14K50-ISS.pdf
(4 pages)
Specifications of PIC18F14K50T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
15
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
A/d Bit Size
10 bit
A/d Channels Available
11
Height
2.05 mm
Length
12.8 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7.49 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC244023 - PROC EXTENS PAK PIC18F1XK50DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOIC
Lead Free Status / Rohs Status
Details
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F14K50-ISS PDF datasheet #4
- Current page: 170 of 420
- Download datasheet (4Mb)
PIC18F/LF1XK50
15.3.9
A Repeated Start condition occurs when the RSEN bit
of the SSPCON2 register is programmed high and the
I
is set, the SCL pin is asserted low. When the SCL pin
is sampled low, the Baud Rate Generator is loaded and
begins counting. The SDA pin is released (brought
high) for one Baud Rate Generator count (T
the Baud Rate Generator times out, if SDA is sampled
high, the SCL pin will be deasserted (brought high).
When SCL is sampled high, the Baud Rate Generator
is reloaded and begins counting. SDA and SCL must
be sampled high for one T
lowed by assertion of the SDA pin (SDA = 0) for one
T
the SSPCON2 register will be automatically cleared
and the Baud Rate Generator will not be reloaded,
leaving the SDA pin held low. As soon as a Start condi-
tion is detected on the SDA and SCL pins, the S bit of
the SSPSTAT register will be set. The SSPIF bit will not
be set until the Baud Rate Generator has timed out.
FIGURE 15-20:
DS41350E-page 170
2
BRG
C logic module is in the Idle state. When the RSEN bit
while SCL is high. Following this, the RSEN bit of
I
START CONDITION TIMING
2
C MASTER MODE REPEATED
on falling edge of ninth clock,
RSEN bit set by hardware
REPEAT START CONDITION WAVEFORM
SDA
SCL
BRG
end of Xmit
. This action is then fol-
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change).
BRG
). When
Preliminary
T
SDA = 1,
SCL = 1
BRG
T
BRG
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After the
first eight bits are transmitted and an ACK is received,
the user may then transmit an additional eight bits of
address (10-bit mode) or eight bits of data (7-bit mode).
15.3.9.1
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Note 1: If RSEN is programmed while any other
Sr = Repeated Start
T
BRG
2: A bus collision during the Repeated Start
At completion of Start bit,
hardware clears RSEN bit
S bit set by hardware
and sets SSPIF
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
Write to SSPBUF occurs here
event is in progress, it will not take effect.
condition occurs if:
• SDA is sampled low when SCL goes
• SCL goes low before SDA is
WCOL Status Flag
T
from low-to-high.
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
BRG
1st bit
T
BRG
2010 Microchip Technology Inc.
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