PIC16LF1847-E/ML Microchip Technology, PIC16LF1847-E/ML Datasheet - Page 97
![14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan](/photos/40/79/407995/pdip18_sml.jpg)
PIC16LF1847-E/ML
Manufacturer Part Number
PIC16LF1847-E/ML
Description
14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet
1.PIC16F1847-EP.pdf
(408 pages)
Specifications of PIC16LF1847-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad
Core
PIC
Processor Series
PIC16LF
Data Bus Width
8 bit
Maximum Clock Frequency
32 MHz
Data Ram Size
256 B
Number Of Programmable I/os
15
Number Of Timers
ÿ4 x 8-bit, 1 x 16-bit
Operating Supply Voltage
1.8 V to 5.5 V
Mounting Style
Through Hole
Interface Type
SPI, I2C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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8.5.9
The PIR4 register contains the interrupt flag bits, as
shown in
REGISTER 8-9:
TABLE 8-1:
2011 Microchip Technology Inc.
INTCON
OPTION_REG
PIE1
PIE2
PIE3
PIE4
PIR1
PIR2
PIR3
PIR4
Legend:
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-2
bit 1
bit 0
Name
U-0
—
Register
— = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.
PIR4 REGISTER
Unimplemented: Read as ‘0’
BCL2IF: MSSP2 Bus Collision Interrupt Flag bit
1 = A Bus Collision was detected (must be cleared in software)
0 = No Bus collision was detected
SSP2IF: Master Synchronous Serial Port 2 (MSSP2) Interrupt Flag bit
1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software)
0 = Waiting to Transmit/Receive/Bus Condition in progress
TMR1GIE
TMR1GIF
WPUEN
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
8-9.
OSFIE
OSFIF
Bit 7
GIE
—
—
—
—
U-0
—
PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4
INTEDG
PEIE
ADIE
C2IE
ADIF
Bit 6
C2IF
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
—
—
—
—
U-0
—
TMR0CS
TMR0IE
CCP4IE
CCP4IF
RCIE
C1IE
RCIF
Bit 5
C1IF
—
—
U-0
Preliminary
—
TMR0SE
CCP3IE
CCP3IF
INTE
TXIE
EEIE
Bit 4
TXIF
EEIF
—
—
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware
TMR6IE
SSP1IE
TMR6IF
BCL1IE
SSP1IF
BCL1IF
U-0
IOCE
Bit 3
PSA
—
—
—
Note 1: Interrupt flag bits are set when an inter-
TMR0IF
CCP1IE
CCP1IF
Bit 2
PS2
rupt condition occurs, regardless of the
state of its corresponding enable bit or
the Global Enable bit, GIE of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
—
—
—
—
—
—
U-0
PIC16(L)F1847
—
TMR2IE
TMR4IE
TMR2IF
TMR4IF
BCL2IE
BCL2IF
Bit 1
INTF
PS1
—
—
R/W/HS-0/0
BCL2IF
TMR1IE
CCP2IE
TMR1IF
CCP2IF
SSP2IE
SSP2IF
IOCF
Bit 0
PS0
—
—
DS41453B-page 97
R/W/HS-0/0
SSP2IF
Register
on Page
177
89
90
91
92
93
94
95
96
97
bit 0
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