PIC16LF1847-E/ML Microchip Technology, PIC16LF1847-E/ML Datasheet - Page 141
![14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan](/photos/40/79/407995/pdip18_sml.jpg)
PIC16LF1847-E/ML
Manufacturer Part Number
PIC16LF1847-E/ML
Description
14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet
1.PIC16F1847-EP.pdf
(408 pages)
Specifications of PIC16LF1847-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad
Core
PIC
Processor Series
PIC16LF
Data Bus Width
8 bit
Maximum Clock Frequency
32 MHz
Data Ram Size
256 B
Number Of Programmable I/os
15
Number Of Timers
ÿ4 x 8-bit, 1 x 16-bit
Operating Supply Voltage
1.8 V to 5.5 V
Mounting Style
Through Hole
Interface Type
SPI, I2C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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TABLE 16-1:
FIGURE 16-2:
2011 Microchip Technology Inc.
Legend:
Note 1:
Clock Source
ADC Clock Period (T
Fosc/16
Fosc/32
Fosc/64
Fosc/2
Fosc/4
Fosc/8
ADC
F
2:
3:
4:
RC
T
Set GO bit
CY
Holding capacitor is disconnected from analog input (typically 100 ns)
Shaded cells are outside of recommended range.
The F
These values violate the minimum required T
For faster conversion times, the selection of another clock source is recommended.
The ADC clock period (T
system clock F
device in Sleep mode.
- T
AD
Conversion starts
RC
ADCS<2:0>
ADC CLOCK PERIOD (T
T
AD
source has a typical T
000
100
001
101
010
110
x11
1 T
ANALOG-TO-DIGITAL CONVERSION T
AD
OSC
)
AD
b9
. However, the F
2 T
1.0-6.0 s
0.5 s
62.5ns
125 ns
AD
32 MHz
AD
b8
800 ns
1.0 s
2.0 s
3 T
) and total ADC conversion time can be minimized when the ADC clock is derived from the
(2)
(2)
(2)
AD
AD
(1,4)
b7
time of 1.6 s for V
4 T
RC
1.0-6.0 s
clock source must be used when conversions are to be performed with the
AD
AD
b6
100 ns
200 ns
400 ns
20 MHz
800 ns
5 T
1.6 s
3.2 s
) V
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Preliminary
AD
S
AD
(2)
(2)
(2)
b5
. DEVICE OPERATING FREQUENCIES
time.
(1,4)
6 T
DD
AD
1.0-6.0 s
b4
.
Device Frequency (F
125 ns
250 ns
7 T
0.5 s
16 MHz
1.0 s
2.0 s
4.0 s
AD
b3
(2)
(2)
(2)
AD
8
(1,4)
CYCLES
T
AD
b2
1.0-6.0 s
9 T
250 ns
500 ns
8.0 s
8 MHz
1.0 s
2.0 s
4.0 s
AD
PIC16(L)F1847
b1
OSC
10
(3)
(2)
(2)
(1,4)
)
T
AD
b0
11
1.0-6.0 s
16.0 s
500 ns
8.0 s
4 MHz
1.0 s
2.0 s
4.0 s
(3)
(2)
(3)
(1,4)
DS41453B-page 141
1.0-6.0 s
16.0 s
32.0 s
64.0 s
8.0 s
1 MHz
2.0 s
4.0 s
(3)
(3)
(3)
(3)
(1,4)
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