PIC16LF1828-E/SO Microchip Technology, PIC16LF1828-E/SO Datasheet - Page 76
![7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core, Nan](/photos/28/72/287224/20-soic_sot163-1_sml.jpg)
PIC16LF1828-E/SO
Manufacturer Part Number
PIC16LF1828-E/SO
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core, Nan
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F1824-ISL.pdf
(419 pages)
Specifications of PIC16LF1828-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (0.300", 7.50mm Width)
Processor Series
PIC16LF
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16(L)F1824/1828
REGISTER 6-1:
DS41419B-page 76
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4-3
bit 2-0
Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.
CLKREN
R/W-0/0
2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%
3: To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration
is selected.
Word 1 = 0 will result in F
CLKREN: Reference Clock Module Enable bit
1 = Reference Clock module is enabled
0 = Reference Clock module is disabled
CLKROE: Reference Clock Output Enable bit
1 = Reference Clock output is enabled on CLKR pin
0 = Reference Clock output disabled on CLKR pin
CLKRSLR: Reference Clock Slew Rate Control Limiting Enable bit
1 = Slew Rate limiting is enabled
0 = Slew Rate limiting is disabled
CLKRDC<1:0>: Reference Clock Duty Cycle bits
11 = Clock outputs duty cycle of 75%
10 = Clock outputs duty cycle of 50%
01 = Clock outputs duty cycle of 25%
00 = Clock outputs duty cycle of 0%
CLKRDIV<2:0> Reference Clock Divider bits
111 = Base clock value divided by 128
110 = Base clock value divided by 64
101 = Base clock value divided by 32
100 = Base clock value divided by 16
011 = Base clock value divided by 8
010 = Base clock value divided by 4
001 = Base clock value divided by 2
000 = Base clock value
CLKROE
R/W-0/0
CLKRCON: REFERENCE CLOCK CONTROL REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
CLKRSLR
R/W-1/1
OSC
(2)
/4. See
R/W-1/1
Section 6.3 “Conflicts with the CLKR pin”
Preliminary
CLKRDC<1:0>
(1)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
(3)
R/W-0/0
R/W-0/0
2010 Microchip Technology Inc.
CLKRDIV<2:0>
R/W-0/0
for details.
R/W-0/0
bit 0
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