PIC16LF1828-E/SO Microchip Technology, PIC16LF1828-E/SO Datasheet - Page 114
![7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core, Nan](/photos/28/72/287224/20-soic_sot163-1_sml.jpg)
PIC16LF1828-E/SO
Manufacturer Part Number
PIC16LF1828-E/SO
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core, Nan
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F1824-ISL.pdf
(419 pages)
Specifications of PIC16LF1828-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (0.300", 7.50mm Width)
Processor Series
PIC16LF
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16(L)F1824/1828
EXAMPLE 11-4:
DS41419B-page 114
; This row erase routine assumes the following:
; 1. A valid address within the erase block is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BSF
BCF
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BCF
BSF
ERASING ONE ROW OF PROGRAM MEMORY
INTCON,GIE
EEADRL
ADDRL,W
EEADRL
ADDRH,W
EEADRH
EECON1,EEPGD
EECON1,CFGS
EECON1,FREE
EECON1,WREN
55h
EECON2
0AAh
EECON2
EECON1,WR
EECON1,WREN
INTCON,GIE
; Disable ints so required sequences will execute properly
; Load lower 8 bits of erase address boundary
; Load upper 6 bits of erase address boundary
; Point to program memory
; Not configuration space
; Specify an erase operation
; Enable writes
; Start of required sequence to initiate erase
; Write 55h
;
; Write AAh
; Set WR bit to begin erase
; Any instructions here are ignored as processor
; halts to begin erase sequence
; Processor will stop here and wait for erase complete.
; after erase processor continues with 3rd instruction
; Disable writes
; Enable interrupts
Preliminary
2010 Microchip Technology Inc.
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