PIC16LF1828-E/SO Microchip Technology, PIC16LF1828-E/SO Datasheet - Page 141
![7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core, Nan](/photos/28/72/287224/20-soic_sot163-1_sml.jpg)
PIC16LF1828-E/SO
Manufacturer Part Number
PIC16LF1828-E/SO
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core, Nan
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F1824-ISL.pdf
(419 pages)
Specifications of PIC16LF1828-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (0.300", 7.50mm Width)
Processor Series
PIC16LF
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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13.0
The PORTA pins can be configured to operate as
Interrupt-On-Change (IOC) pins. On the PIC16F/LF1828
devices, the PORTB pins can also be configured to
operate as IOC pins. An interrupt can be generated by
detecting a signal that has either a rising edge or a falling
edge. Any individual port pin, or combination of port pins,
can be configured to generate an interrupt. The
interrupt-on-change module has the following features:
• Interrupt-on-change enable (Master Switch)
• Individual pin configuration
• Rising and falling edge detection
• Individual pin interrupt flags
Figure 13-1
13.1
To allow individual port pins to generate an interrupt, the
IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
13.2
For each port pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a
rising edge, the associated bit of the IOCxP register is
set. To enable a pin to detect a falling edge, the
associated bit of the IOCxN register is set.
A pin can be configured to detect rising and falling
edges simultaneously by setting both associated bits of
the IOCxP and IOCxN registers, respectively.
FIGURE 13-1:
2010 Microchip Technology Inc.
RAx
INTERRUPT-ON-CHANGE
Enabling the Module
Individual Pin Configuration
is a block diagram of the IOC module.
IOCANx
IOCAPx
INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)
D
CK
D
CK
R
R
Q
Q
Preliminary
Q2 Clock Cycle
individual pin detectors
From all other IOCAFx
13.3
The IOCAFx and IOCBFx bits located in the IOCAF and
IOCBF registers, respectively, are status flags that
correspond to the interrupt-on-change pins of the
associated port. If an expected edge is detected on an
appropriately enabled pin, then the status flag for that pin
will be set, and an interrupt will be generated if the IOCIE
bit is set. The IOCIF bit of the INTCON register reflects
the status of all IOCAFx and IOCBFx bits.
13.4
The individual status flags, (IOCAFx and IOCBFx bits),
can be cleared by resetting them to zero. If another edge
is detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
EXAMPLE 13-1:
13.5
The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCxF
register will be updated prior to the first instruction
executed out of Sleep.
IOCAFx
PIC16(L)F1824/1828
ANDWF
MOVLW
XORWF
Interrupt Flags
Clearing Interrupt Flags
Operation in Sleep
0xff
IOCAF, W
IOCAF, F
IOCIE
DS41419B-page 141
IOC Interrupt to
CPU Core
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