PIC16F1847-I/SO Microchip Technology, PIC16F1847-I/SO Datasheet - Page 285

• Manufacturer Part Number: PIC16F1847-I/SO
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core 18 S
• Manufacturer: Microchip Technology

Specifications of PIC16F1847-I/SO

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 25-4:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
ACKTIM
R-0/0
2:
3:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.
This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
ACKTIM: Acknowledge Time Status bit (I
1 = Indicates the I
0 = Not an Acknowledge sequence, cleared on 9
PCIE: Stop Condition Interrupt Enable bit (I
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
SCIE: Start Condition Interrupt Enable bit (I
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:
In I
In I
SDAHT: SDAx Hold Time Selection bit (I
1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
SBCDE: Slave Mode Bus Collision Detect Enable bit (I
If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the
BCLxIF bit of the PIR2 register is set, and bus goes Idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
AHEN: Address Hold Enable bit (I
1 = Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the
0 = Address holding is disabled
DHEN: Data Hold Enable bit (I
1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit
0 = Data holding is disabled
R/W-0/0
2
2
PCIE
C Master mode and SPI Master mode:
C Slave mode:
This bit is ignored.
1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the
1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the
0 = SSPxBUF is only updated when SSPOV is clear
SSPxCON1 register will be cleared and the SCLx will be held low.
of the SSPxCON1 register and SCLx is held low.
SSPxCON3: SSPx CONTROL REGISTER 3
SSPxCON1 register is set, and the buffer is not updated
state of the SSPOV bit only if the BF bit = 0.
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
2
SCIE
C bus is in an Acknowledge sequence, set on 8
(1)
2
R/W-0/0
C Slave mode only)
BOEN
2
Preliminary
C Slave mode only)
2
2
(2)
(2)
C mode only)
C mode only)
2
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
2
C mode only)
C mode only)
R/W-0/0
SDAHT
TH
rising edge of SCLx clock
2
(3)
C Slave mode only)
R/W-0/0
SBCDE
PIC16(L)F1847
TH
falling edge of SCLx clock
R/W-0/0
AHEN
DS41453A-page 285
R/W-0/0
DHEN
bit 0