PIC16F1847-I/SO Microchip Technology, PIC16F1847-I/SO Datasheet - Page 213

• Manufacturer Part Number: PIC16F1847-I/SO
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core 18 S
• Manufacturer: Microchip Technology

Specifications of PIC16F1847-I/SO

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.3.7
In Sleep mode, the TMRx register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMRx will continue from its
previous state.
24.3.8
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)”
24.3.9
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
TABLE 24-8:
 2011 Microchip Technology Inc.
APFCON0
CCP1CON
CCPTMRS
CCP2CON
PR4
PR6
T4CON
TMR4
T6CON
TMR6
CCP3CON
CCP4CON
INTCON
PR2
T2CON
TMR2
TRISB
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the PWM.
Name
*
Page provides register information.
OPERATION IN SLEEP MODE
CHANGES IN SYSTEM CLOCK
FREQUENCY
EFFECTS OF RESET
Timer4 Period Register
Timer6 Period Register
Holding Register for the 8-bit TMR4 Time Base
Holding Register for the 8-bit TMR6 Time Base
Timer2 Period Register
Holding Register for the 8-bit TMR2 Time Base
RXDTSEL
TRISB7
Bit 7
GIE
for additional details.
—
—
—
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH PWM
C4TSEL<1:0>
P1M<1:0>
P2M<1:0>
SDO1SEL
TRISB6
PEIE
Bit 6
—
—
SS1SEL
TMR0IE
TRISB5
Bit 5
T4OUTPS<3:0>
T6OUTPS<3:0>
T2OUTPS<3:0>
C3TSEL<1:0>
DC1B<1:0>
DC2B<1:0>
DC3B<1:0>
DC4B<1:0>
P2BSEL
TRISB4
Preliminary
INTE
Bit 4
CCP2SEL
TRISB3
IOCE
24.3.10
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
registers, APFCON0 and APFCON1. To determine
which pins can be moved and what their default loca-
tions are upon a Reset, see
Pin Function”
Bit 3
C2TSEL<1:0>
TMR4ON
TRM6ON
TMR2ON
P1DSEL
TMR0IF
TRISB2
ALTERNATE PIN LOCATIONS
Bit 2
CCP1M<3:0>
CCP2M<3:0>
CCP3M<3:0>
CCP4M<3:0>
for more information.
PIC16(L)F1847
P1CSEL
TRISB1
INTF
Bit 1
T4CKPS<1:0>
T6CKPS<1:0>
T2CKPS<1:0>
C1TSEL<1:0>
Section 12.1 “Alternate
CCP1SEL
TRISB0
IOCF
Bit 0
DS41453A-page 213
Register
on Page
191*
191*
120
228
229
228
193
193
228
228
193
127
92
92
92
92
89