PIC16F1507-E/ML Microchip Technology, PIC16F1507-E/ML Datasheet - Page 78
![3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm TUBE](/photos/16/3/160361/qfn20_sml.jpg)
PIC16F1507-E/ML
Manufacturer Part Number
PIC16F1507-E/ML
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F1507-EML.pdf
(266 pages)
2.PIC16F1507-EML.pdf
(26 pages)
3.PIC16F1507-EML.pdf
(40 pages)
Specifications of PIC16F1507-E/ML
Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
- Current page: 78 of 266
- Download datasheet (3Mb)
REGISTER 8-1:
TABLE 8-1:
2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-2
bit 1
bit 0
Note 1:
Name
INTCON
IOCAF
IOCAN
IOCAP
IOCBF
IOCBN
IOCBP
PIE1
PIE2
PIR1
PIR2
STATUS
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode.
U-0
—
PIC16F1507 only.
TMR1GIE
TMR1GIF
IOCBF7
IOCBN7
IOCBP7
Bit 7
GIE
Unimplemented: Read as ‘0’
VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep
0 = Normal Power mode enabled in Sleep
Reserved: Read as ‘1’. Maintain this bit set.
—
—
—
—
—
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Draws lowest current in Sleep, slower wake-up
Draws higher current in Sleep, faster wake-up
U-0
—
VREGCON: VOLTAGE REGULATOR CONTROL REGISTER
IOCBN6
IOCBF6
IOCBP6
PEIE
ADIE
ADIF
Bit 6
—
—
—
—
—
—
—
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
TMR0IE
IOCAF5
IOCAN5
IOCAP5
IOCBF5
IOCBN5
IOCBP5
—
Bit 5
—
—
—
—
—
IOCAN4
IOCAP4
IOCBN4
IOCBP4
IOCAF4
IOCBF4
INTE
Bit 4
U-0
TO
—
—
—
—
Preliminary
—
WDTPS<4:0>
IOCAN3
IOCAF3
IOCAP3
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
IOCIE
Bit 3
PD
—
—
—
—
—
—
—
U-0
—
TMR0IF
IOCAN2
IOCAP2
NCO1IE
NCO1IF
IOCAF2
Bit 2
—
—
—
—
—
Z
U-0
PIC16(L)F1507
—
IOCAN1
IOCAP1
TMR2IE
IOCAF1
TMR2IF
Bit 1
INTF
DC
—
—
—
—
—
VREGPM
R/W-0/0
(1)
SWDTEN
IOCAN0
IOCAF0
IOCAP0
TMR1IE
TMR1IF
IOCIF
Bit 0
—
—
—
—
—
C
DS41586A-page 78
Register on
Reserved
R/W-1/1
Page
113
113
113
114
114
114
66
67
68
70
71
18
81
bit 0
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