PIC16F1507-E/ML Microchip Technology, PIC16F1507-E/ML Datasheet - Page 161
![3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm TUBE](/photos/16/3/160361/qfn20_sml.jpg)
PIC16F1507-E/ML
Manufacturer Part Number
PIC16F1507-E/ML
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F1507-EML.pdf
(266 pages)
2.PIC16F1507-EML.pdf
(26 pages)
3.PIC16F1507-EML.pdf
(40 pages)
Specifications of PIC16F1507-E/ML
Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
- Current page: 161 of 266
- Download datasheet (3Mb)
PIC16(L)F1507
20.0
The Configurable Logic Cell (CLCx) provides program-
mable logic that operates outside the speed limitations
of software execution. The logic cell takes up to 16
input signals and through the use of configurable gates
reduces the 16 inputs to four logic lines that drive one
of eight selectable single-output logic functions.
Input sources are a combination of the following:
• I/O pins
• Internal clocks
• Peripherals
• Register bits
The output can be directed internally to peripherals and
to an output pin.
FIGURE 20-1:
DS41586A-page 161
CLCxIN[10]
CLCxIN[12]
CLCxIN[13]
CLCxIN[14]
CLCxIN[15]
CLCxIN[11]
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
CLCxIN[8]
CLCxIN[9]
CONFIGURABLE LOGIC CELL
(CLC)
See
Figure 20-2
CLCx SIMPLIFIED BLOCK DIAGRAM
lcxg1
lcxg2
lcxg3
lcxg4
See
LCxMODE<2:0>
Function
Figure 20-3
Logic
lcxq
LCxEN
Preliminary
LCxPOL
Refer to
signal flow through the CLCx.
Possible configurations include:
• Combinatorial Logic
• Latches
- AND
- NAND
- AND-OR
- AND-OR-INVERT
- OR-XOR
- OR-XNOR
- S-R
- Clocked D with Set and Reset
- Transparent D with Set and Reset
- Clocked J-K with Reset
Figure 20-1
LCxINTP
LCxINTN
lcx_out
Interrupt
Interrupt
det
det
Q1
for a simplified diagram showing
2011 Microchip Technology Inc.
D
LE
LCxOE
Q
TRIS Control
LCxOUT
MLCxOUT
CLCx
CLCxIF
sets
flag
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