PIC16F1507-E/ML Microchip Technology, PIC16F1507-E/ML Datasheet - Page 137
![3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm TUBE](/photos/16/3/160361/qfn20_sml.jpg)
PIC16F1507-E/ML
Manufacturer Part Number
PIC16F1507-E/ML
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F1507-EML.pdf
(266 pages)
2.PIC16F1507-EML.pdf
(26 pages)
3.PIC16F1507-EML.pdf
(40 pages)
Specifications of PIC16F1507-E/ML
Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
- Current page: 137 of 266
- Download datasheet (3Mb)
PIC16(L)F1507
16.2
REGISTER 16-1:
TABLE 16-1:
DS41586A-page 137
ADCON2
INTCON
OPTION_REG
TMR0
TRISA
Legend:
Note 1:
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
R/W-1/1
WPUEN
Name
*
Option and Timer0 Control Register
— = Unimplemented location, read as ‘ 0 ’. Shaded cells are not used by the Timer0 module.
Page provides register information.
Unimplemented, read as ‘ 1 ’.
Holding Register for the 8-bit Timer0 Count
WPUEN: Weak Pull-Up Enable bit
1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (F
TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
WPUEN
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
INTEDG
R/W-1/1
Bit 7
GIE
—
OPTION_REG: OPTION REGISTER
Bit Value
INTEDG
000
001
010
011
100
101
110
111
Bit 6
PEIE
TRIGSEL<3:0>
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
—
TMR0CS
R/W-1/1
Timer0 Rate
TMR0CS
TMR0IE
TRISA5
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit 5
TMR0SE
R/W-1/1
TMR0SE
TRISA4
Preliminary
INTE
Bit 4
OSC
/4)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-1/1
IOCIE
Bit 3
PSA
PSA
—
—
(1)
TMR0IF
TRISA2
Bit 2
R/W-1/1
—
PS<2:0>
TRISA1
2011 Microchip Technology Inc.
Bit 1
INTF
—
PS<2:0>
R/W-1/1
TRISA0
IOCIF
Bit 0
—
R/W-1/1
Register
on Page
135*
129
137
102
66
bit 0
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