XC3SD3400A-4FGG676C Xilinx Inc, XC3SD3400A-4FGG676C Datasheet - Page 68

• Manufacturer Part Number: XC3SD3400A-4FGG676C
• Description: FPGA, SPARTAN-3A, DSP, 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4FGG676C

• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 2322432
• No. Of I/o's: 502
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Number Of I /o: 469
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Package: 676FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 469
• Ram Bits: 2322432
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1539

Table 63: Spartan-3A DSP CS484 Pinout (Cont’d)
DS610 (v3.0) October 4, 2010
Product Specification
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L03N_1/A1
IP_L08P_1
IO_L03P_1/A0
IP_L04N_1/VREF_1
IP_L04P_1
IO_L06P_1
IO_L02P_1/LDC1
IO_L06N_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IO_L01P_2/M1
IO_L04N_2
IP_2
IO_L08N_2
IO_L12N_2/D6
IO_L16P_2/GCLK14
IO_L18N_2/GCLK3
IO_L19P_2
IO_L22P_2/AWAKE
IO_L27N_2
IO_L30P_2
IP_2/VREF_2
IO_L01N_2/M0
IO_L04P_2
IO_L05P_2
IO_L05N_2
IO_L08P_2
IO_L09P_2/VS1
IO_L09N_2/VS0
IO_L12P_2/D7
IP_2/VREF_2
IO_L16N_2/GCLK15
IO_L18P_2/GCLK2
IO_L19N_2
IP_2
IO_L22N_2/DOUT
IO_L23P_2
IO_L23N_2
Pin Name
V20
V22
W19
W20
W21
W22
Y21
Y22
E21
J18
K21
P18
P21
V21
AA3
AA4
AA6
AA8
AA10
AA12
AA14
AA15
AA17
AA19
AA20
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
CS484
Ball
PWRMGMT
DUAL
INPUT
DUAL
VREF
INPUT
I/O
DUAL
I/O
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
I/O
INPUT
I/O
DUAL
GCLK
GCLK
I/O
I/O
I/O
VREF
DUAL
I/O
I/O
I/O
I/O
DUAL
DUAL
DUAL
VREF
GCLK
GCLK
I/O
INPUT
DUAL
I/O
I/O
Type
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Table 63: Spartan-3A DSP CS484 Pinout (Cont’d)
Bank
Spartan-3A DSP FPGA Family: Pinout Descriptions
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L27P_2
IO_L30N_2
IO_L02N_2/CSO_B
IO_L11N_2
IO_L10N_2
IO_L14N_2/D4
IO_L17P_2/GCLK0
IO_L20P_2
IO_L25P_2
IO_L25N_2
IO_L28P_2
IO_L02P_2/M2
IO_L11P_2
IO_L06N_2
IO_L10P_2
IO_L14P_2/D5
IO_L17N_2/GCLK1
IO_L20N_2/MOSI/CSI_B
IP_2/VREF_2
IO_L28N_2
IO_L31N_2/CCLK
IP_2/VREF_2
IO_L03P_2
IO_L07N_2/VS2
IO_L06P_2
IP_2/VREF_2
IP_2
IP_2/VREF_2
IO_L21N_2
IO_L24P_2/INIT_B
IO_L31P_2/D0/DIN/MISO
IP_2/VREF_2
IO_L03N_2
IO_L07P_2/RDWR_B
IP_2
IP_2
IO_L13P_2
IO_L13N_2
IO_L15N_2/GCLK13
IO_L15P_2/GCLK12
IP_2
IO_L21P_2
Pin Name
AB19
AB20
U7
U8
U9
U10
U12
U13
U14
U15
U16
V6
V7
V8
V10
V11
V12
V13
V15
V16
V17
W4
W5
W6
W8
W9
W10
W13
W14
W15
W17
W18
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
CS484
Ball
I/O
I/O
DUAL
I/O
I/O
DUAL
GCLK
I/O
I/O
I/O
I/O
DUAL
I/O
I/O
I/O
DUAL
GCLK
DUAL
VREF
I/O
DUAL
VREF
I/O
DUAL
I/O
VREF
INPUT
VREF
I/O
DUAL
DUAL
VREF
I/O
DUAL
INPUT
INPUT
I/O
I/O
GCLK
GCLK
INPUT
I/O
Type
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