XC3SD3400A-4FGG676C Xilinx Inc, XC3SD3400A-4FGG676C Datasheet - Page 21

• Manufacturer Part Number: XC3SD3400A-4FGG676C
• Description: FPGA, SPARTAN-3A, DSP, 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4FGG676C

• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 2322432
• No. Of I/o's: 502
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Number Of I /o: 469
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Package: 676FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 469
• Ram Bits: 2322432
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1539

Pin-to-Pin Setup and Hold Times
Table 18: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
3.
4.
Setup Times
Hold Times
The numbers in this table are tested using the methodology presented in
Table 7
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from
appropriate Input adjustment from the same table.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
DCM output jitter is included in all measurements.
Symbol
T
T
T
T
PSDCM
PHDCM
PHFD
PSFD
and
Table
When writing to the Input
Flip-Flop (IFF), the time from
the setup of data at the Input pin
to the active transition at a
Global Clock pin. The DCM is in
use. No Input Delay is
programmed.
When writing to IFF, the time
from the setup of data at the
Input pin to an active transition
at the Global Clock pin. The
DCM is not in use. The Input
Delay is programmed.
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is in use.
No Input Delay is programmed.
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is not in
use. The Input Delay is
programmed.
10.
Description
LVCMOS25
IFD_DELAY_VALUE = 0,
with DCM
LVCMOS25
IFD_DELAY_VALUE = 6,
without DCM
LVCMOS25
IFD_DELAY_VALUE = 0,
with DCM
LVCMOS25
IFD_DELAY_VALUE = 6,
without DCM
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Conditions
(4)
(4)
(2)
(2)
(3)
(3)
,
,
,
,
Table 26
and are based on the operating conditions set forth in
XC3SD1800A
XC3SD3400A
XC3SD1800A
XC3SD3400A
XC3SD1800A
XC3SD3400A
XC3SD1800A
XC3SD3400A
Table
Table
Device
22. If this is true of the data Input, subtract the
22. If this is true of the data Input, add the
–0.38
–0.26
–0.71
–0.65
Max
2.65
2.25
2.98
2.78
-5
Speed Grade
–0.38
–0.26
–0.71
–0.65
Max
3.11
2.49
3.39
3.08
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
21