PEB3264F-V1.4 Infineon Technologies, PEB3264F-V1.4 Datasheet - Page 277

• Manufacturer Part Number: PEB3264F-V1.4
• Manufacturer: Infineon Technologies

Specifications of PEB3264F-V1.4

• Lead Free Status / RoHS Status: Not Compliant

Preliminary
Bit
After a hardware reset the RSTAT bit is set and generates an interrupt. Therefore the
default value of INTREG2 is 20h. After reading all four interrupt registers, the INTREG2
value changes to 4Fh.
READY
RSTAT
IO[4:1]-DU
Bit
Bit
Data Sheet
08
09
0A
H
H
H
INTREG2
INTREG3
INTREG4
7
0
7
0
7
0
Data on IO pins 1 to 4 filtered by the DUP-IO counter and interrupt
generation masked by the IO[4:1]-DU-M bits. A change of any of these
bits generates an interrupt.
Reset status since last interrupt.
RSTAT = 0
RSTAT = 1
Indication whether ramp generator has finished. An interrupt is only
generated if the READY bit changes from 0 to 1. At a new start of the
ramp generator, the bit is set to 0. For further information regarding soft
reversal see
READY = 0
READY = 1
READY RSTAT
6
6
0
6
0
Interrupt Register 2 (read-only)
Interrupt Register 3 (read-only)
Interrupt Register 4 (read-only)
Chapter
Ramp generator active.
Ramp generator not active.
No reset has occurred since the last interrupt.
Reset has occurred since the last interrupt.
5
5
0
5
0
SLICOFI-2x Command Structure and Programming
3.7.2.1.
4
0
4
0
4
0
277
3
3
0
3
0
2
IO[4:1]-DU
2
0
2
0
20
00
00
H
H
H
DuSLIC-S/-S2
1
1
0
1
0
2000-07-14
0
0
0
0
0
Y
Y
Y