PEB3264F-V1.4 Infineon Technologies, PEB3264F-V1.4 Datasheet - Page 164

• Manufacturer Part Number: PEB3264F-V1.4
• Manufacturer: Infineon Technologies

Specifications of PEB3264F-V1.4

• Lead Free Status / RoHS Status: Not Compliant

Preliminary
Table 47
Command/Indication
Operation (CIOP)
M2
1
0
0
1
1
1
0
ADR[2:0]
CMD[2:0] Command for programming the SLICOFI-2x (OP = 1) or command
Data Sheet
M1
1
0
1
0
1
0
0
equivalent to the CIDD channel bits M[2:0] in microcontroller interface mode
(OP = 0)
The first four commands have no second command byte following.
All necessary information is present in the first command byte.
CMD[2:0] = 0 0 0
CMD[2:0] = 0 0 1
CMD[2:0] = 0 1 0
CMD[2:0] = 0 1 1
The second four commands are followed by a second command byte which
defines additional information, e.g., specifying sub-adresses of the CRAM.
CMD[2:0] = 1 0 0
CMD[2:0] = 1 0 1
Channel address for the subsequent data
ADR[2:0] = 0 0 0
ADR[2:0] = 0 0 1
(other codes reserved for future use)
M2, M1, M0: General Operating Mode
M0
1
0
0
1
0
0
1
Soft reset of the chip (Reset routine for all channels will
reset all configuration registers, CRAM data is not
affected).
Soft reset for the specified channel A or B in ADR field
Resychronization of the PCM interface
(only available when pin PCM/IOM-2 = 1)
reserved for future use
SOP command (status operation, programming and
monitoring of all status-relevant data).
COP command (coefficient operation, programming
and monitoring of all coefficients in the CRAM).
SLICOFI-2x Command Structure and Programming
SLICOFI-2x Operating Mode
(for details see
Chip Set” on Page
Sleep, Power Down (PDRx)
Power Down High Impedance (PDH)
Any Active mode
Ringing (ACTR Burst On)
Active with Metering
Ground Start
Ring Pause
Channel A
Channel B
164
“Operating Modes for the DuSLIC
78)
2000-07-14
DuSLIC