1892YLF IDT, Integrated Device Technology Inc, 1892YLF Datasheet - Page 19

• Manufacturer Part Number: 1892YLF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 1892YLF

• Lead Free Status / RoHS Status: Compliant

5.1.2 Specific Reset Operations
5.1.2.1 Hardware Reset
5.1.2.2 Power-On Reset
ICS1892, Rev. D, 2/26/01
This section discusses the following specific ways that the ICS1892 can be reset:
•
•
•
Note:
Entering Hardware Reset
Holding the active-low RESET* pin low for a minimum of five REF_IN clock cycles initiates a hardware
reset (that is, the ICS1892 enters the reset state). During reset, the ICS1892 executes the steps listed in
Section 5.1.1.1, “Entering
Exiting Hardware Reset
After the signal on the RESET* pin transitions from a low to a high state, the ICS1892 completes in 640 ns
(that is, in 16 REF_IN clocks) steps 1 through 5, listed in
steps are completed, the Serial Management Port is ready for normal operations, but this action does not
signify the end of the reset cycle. The reset cycle completes when the transmit clock (TXCLK) and receive
clock (RXCLK) are available, which is typically 53 ms after the RESET* pin goes high. [For details on this
transition, see
Note:
1. The MAC/Repeater Interface is not available for use until the TXCLK and RXCLK are valid.
2. The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit
Entering Power-On Reset
When power is applied to the ICS1892, it waits until the potential between V
minimum voltage of 4.5 VDC before entering reset and executing the steps listed in
“Entering
approximately 20 µs. (For details on this transition, see
Exiting Power-On Reset
The ICS1892 automatically exits reset and performs the same steps as for a hardware reset. (See
5.1.1.2, “Exiting
Note:
Hardware reset (using the RESET* pin)
Power-on reset (applying power to the ICS1892)
Software reset (using Control Register bit 0.15)
ICS1892
that is used to initiate a software reset.
At the completion of a reset (either hardware, power-on, or software), the ICS1892 sets all
registers to their default values.
The only difference between a hardware reset and a power-on reset is that during a power-on
reset, the ICS1892 isolates the RESET* input pin. All other functionality is the same. As with a
hardware reset, the Control Register bit 0.15 does not represent the status of a power-on reset.
Reset”. After entering reset from a power-on condition, the ICS1892 remains in reset for
Section 10.5.17, “Reset: Hardware Reset and
Reset”.)
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
Reset”.
19
Section 10.5.16, “Reset: Power-On
Section 5.1.1.2, “Exiting
Power-Down”.]
Chapter 5 Operating Modes Overview
DD
and V
Reset”. After the first five
Section 5.1.1.1,
SS
achieves a
February 26, 2001
Reset”.)
Section