EGLXT973QEA3V Intel, EGLXT973QEA3V Datasheet - Page 19

• Manufacturer Part Number: EGLXT973QEA3V
• Manufacturer: Intel

Specifications of EGLXT973QEA3V

• Lead Free Status / RoHS Status: Compliant

LXT973 PHY Transceiver
Specification Update
249737, Revision 10.0
20 March 2007
Item 2:
Table 4
Item 3:
Table 5
Cortina Systems
Change to Table for Port 0 Signal Descriptions
Port 0 Signal Descriptions
Change to Table for Port 1 Signal Descriptions
Port 1 Signal Descriptions
®
20
20
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
19
19
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
Pin #
Pin #
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down
ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down
MDDIS0
MDDIS0
MDDIS1
MDDIS1
Signal Names
Signal Names
Type
Type
I
I
I
I
1
1
OLD Information in table -
Management Disable. When MDDIS0 is tied High, the MDIO port is
completely disabled and the Hardware Control Interface pins set their
respective bits at power-up and reset.
When MDDIS0 is pulled Low at power-up or reset via the internal pull-
down resistor or by tying it to ground, the Hardware Control Interface
Pins control only the initial or “default” values of their respective
register bits. After the power-up/reset cycle is complete, bit control
reverts to the MDIO serial channel.
UPDATED Information in table -
Management Disable. When MDDIS0 is tied High, the MDIO port is
completely disabled and the Hardware Control Interface pins set their
respective bits at power-up and reset.
When MDDIS0 is pulled low at power-up or reset via an external pull-
down resistor, the Hardware Control Interface Pins control only the
initial values of their respective register bits. After the power-up/reset
cycle is complete, bit control reverts to the MDIO serial channel.
OLD Information in table -
Management Disable. When MDDIS is tied High, the MDIO port is
completely disabled and the Hardware Control Interface pins set their
respective bits at power-up and reset.
When MDDIS is pulled Low at power-up or reset via the internal pull-
down resistor or by tying it to ground, the Hardware Control Interface
Pins control only the initial or “default” values of their respective
register bits. After the power-up/reset cycle is complete, bit control
reverts to the MDIO serial channel.
UPDATED Information in table -
Management Disable. When MDDIS1 is tied High, the MDIO port is
completely disabled and the Hardware Control Interface pins set their
respective bits at power-up and reset.
When MDDIS1 is pulled low at power-up or reset via an external pull-
down resistor, the Hardware Control Interface Pins control only the
initial values of their respective register bits. After the power-up/reset
cycle is complete, bit control reverts to the MDIO serial channel.
Signal Description
Signal Description
8.0 Documentation Changes
Page 19