EGLXT973QEA3V Intel, EGLXT973QEA3V Datasheet - Page 10
![no-image](/images/manufacturer_photos/0/3/336/intel_sml.jpg)
EGLXT973QEA3V
Manufacturer Part Number
EGLXT973QEA3V
Description
Manufacturer
Intel
Datasheet
1.EGLXT973QEA3V.pdf
(20 pages)
Specifications of EGLXT973QEA3V
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EGLXT973QEA3V
Manufacturer:
ALTERA
Quantity:
27
Company:
Part Number:
EGLXT973QEA3V
Manufacturer:
CORTINA
Quantity:
10
Company:
Part Number:
EGLXT973QEA3V-873181
Manufacturer:
Cortina
Quantity:
420
Company:
Part Number:
EGLXT973QEA3V-873181
Manufacturer:
Cortina Systems Inc
Quantity:
10 000
LXT973 PHY Transceiver
Specification Update
249737, Revision 10.0
20 March 2007
5.0
Item 1:
Problem
Implication
Workaround None.
Status
Item 2:
Problem
Implication
Workaround Disable auto MDI/MDIX when in forced 100 Mbps mode.
Status
Item 3:
Problem
Implication
Workaround Configure the LXT973 PHY Transceiver in auto-negotiation rather than forced 100 Mbps
Status
Cortina Systems
Errata
Speed LED Stays Active During Reset
During reset, the speed LED on both ports stays lit. The other LED functions are turned off
during reset. This erratum has been confirmed on all LED modes with the speed function-
ality display while RESET is held active. All other functions such as Link, Activity, Duplex
Status, and MII Isolate turn off during reset.
Monitoring the speed LED during reset may be misleading. The LED functions properly
during normal operation.
There are no plans to fix this erratum.
Delay of Link While in Auto MDI/MDIX Enabled, Forced 100 Mbps
Mode
The LXT973 PHY Transceiver may have difficulty determining the MDI/MDIX setting
under the following conditions:
The LXT973 PHY Transceiver may take several seconds to establish link under the
following conditions:
There are no plans to fix this erratum.
Establishment of Link in Forced 100 Mbps Mode
Link may not come up reliably when the following occurs:
If this condition occurs, communication between the LXT973 PHY Transceiver and its link
partner may not establish. This condition does not occur in other speed setting combina-
tions.
mode, or configure the link partner to forced 100 Mbps instead of auto-negotiation to
establish link.
There are no plans to fix this erratum.
®
• Forced 100 Mbps mode
• Auto MDI/MDIX is enabled
• Link partner is auto-negotiation enabled
• LXT973 PHY Transceiver is forced to 100 Mbps
• Auto MDI/MDIX is enabled
• Link partner is auto-negotiation enabled
• The LXT973 PHY Transceiver is in forced 100 Mbps mode and link is down.
• The link partner is configured to auto-negotiate.
• The link partner cannot handle instantaneous jitter on the MLT3 signal during link-up.
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
5.0 Errata
Page 10