CY7C9689A-AC Cypress Semiconductor Corp, CY7C9689A-AC Datasheet - Page 8

• Manufacturer Part Number: CY7C9689A-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AC

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
Pin Descriptions
6
67
24, 25 RXMODE[1:0] Static control input
77
73
Pin
VLTN
RXRST
RXBISTEN
RFEN
Name
(continued)
Three-state TTL
output, changes
following RXCLK↑
Internal Pull-down
TTL input, sampled on
RXCLK↑
Internal Pull-up
TTL levels
Normally wired HIGH
or LOW
TTL input,
asynchronous
Internal Pull-up
TTL input,
asynchronous
Internal Pull-up
I/O Characteristics
Code Rule Violation Detected.
VLTN is asserted in response to detection of a 4B/5B or 5B/6B character that
does not meet the coding rules of these characters. When VLTN is asserted,
the values on the output DATA and COMMAND buses remain unchanged.
VLTN remains asserted for one RXCLK period.
VLTN is used to report character mismatches when RXBISTEN is driven LOW.
VLTN is driven LOW when the decoder is bypassed (ENCBYP is LOW).
RXEN is a three-state control for VLTN.
Receive FIFO Reset. Active LOW.
When the Receive FIFO is enabled (FIFOBYP is HIGH), RXEN is deasserted,
CE is asserted (LOW), and RXRST is sampled while asserted (LOW) by RXCLK
for seven cycles, the Receive FIFO begins its internal reset process.
Once the reset operation is started, the RXEMPTY flag is asserted and the
interface counters and address pointer are zeroed. The reset operation
proceeds to clear out the internal write pointers and counters. The RXEMPTY
output remains asserted through the reset operation and remains asserted until
new data is written to the Receive FIFO. While RXRST remains asserted, the
Receive FIFO remains in reset and cannot accept received characters.
When the Receive FIFO is bypassed (FIFOBYP is LOW), RXRST is ignored.
Receiver Discard Policy Mode Select.
00b—allows all characters to be written into the Receive FIFO or output to the
Receive data bus
01b—discards all JK or LM sync characters except the “last” one of a string of
sync characters. Single sync characters in a data stream are included in the
data written into the Receive FIFO.
1Xb—discards all JK or LM sync characters. The data stream written into the
Receive FIFO does not include sync characters.
Receiver BIST Enable. Active LOW.
When LOW, the receiver is configured to perform a character-for-character
match of the incoming data stream with a 511-character BIST sequence. The
result of character mismatches are indicated on the VLTN pin. Completion of
each 511-character BIST loop is accompanied by an assertion pulse on the
RXFULL flag.
The state of ENCBYP, FIFOBYP, and BYTE8/10 have no effect on BIST
operation.
Reframe Enable.
Used to control when the framer is allowed to adjust the character boundaries
based on detection of one or more framing characters in the data stream.
When framing is enabled (RFEN is HIGH) the receive framer realigns the serial
stream to the incoming 10-bit JK sync character (if BYTE8/10 is HIGH) or the
12-bit LM sync character (if BYTE8/10 is LOW). Framing is disabled when
RFEN is LOW. The deassertion of RFEN freezes the character boundary
relationship between the serial stream and character clock. RFEN is an
asynchronous input, sampled by the internal Receive PLL character clock.
Signal Description
CY7C9689A
Page 8 of 51
[+] Feedback