CY7C9689A-AC Cypress Semiconductor Corp, CY7C9689A-AC Datasheet - Page 5

• Manufacturer Part Number: CY7C9689A-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AC

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
Pin Descriptions
18
7
16
9
72
Pin
TXEN
TXBISTEN
TXRST
TXHALT
TXFULL
Name
(continued)
TTL input, sampled on
TXCLK↑ or REFCLK↑
Internal Pull-up
TTL input,
asynchronous
Internal Pull-up
TTL input, sampled on
TXCLK↑
Internal Pull-up
TTL input, sampled on
TXCLK↑
Internal Pull-up
Three-state TTL
output, changes
following TXCLK↑ or
REFCLK↑
I/O Characteristics
Transmit Enable.
TXEN is sampled on the rising edge of the TXCLK or REFCLK input and enables
parallel data bus write operations (when selected). The device is selected when
TXEN is asserted during a clock cycle immediately following one in which CE
is sampled LOW.
Depending on the level on EXTFIFO, the asserted state for TXEN can be active
HIGH or active LOW. If EXTFIFO is LOW, then TXEN is active LOW and data
is captured on the same clock cycle where TXEN is sampled LOW. If EXTFIFO
is HIGH, then TXEN is active HIGH and data is captured on the clock cycle
following any clock edge when TXEN is sampled HIGH.
Transmitter BIST Enable.
When TXBISTEN is LOW, the transmitter generates a 511-character repeating
sequence that can be used to validate link integrity. This 4B/5B BIST sequence
is generated regardless of the state of other configuration inputs. The trans-
mitter returns to normal operation when TXBISTEN is HIGH. All Transmit FIFO
read operations are suspended when BIST is active.
Reset Transmit FIFO.
When the Transmit FIFO is enabled (FIFOBYP is HIGH), TXEN is deasserted,
CE is asserted (LOW), and TXRST is sampled LOW by TXCLK for seven cycles,
the Transmit FIFO begins its internal reset process. The Transmit FIFO TXFULL
flag is asserted and the host interface counter and address pointer are zeroed.
This reset propagates to the serial transmit side, any remaining counters and
pointers. The TXFULL flag is asserted until both sides of the Transmit FIFO
have reset. While TXRST remains asserted, the Transmit FIFO remains in reset
and the TXFULL output remains asserted.
When the Transmit FIFO is bypassed (FIFOBYP is LOW), TXRST is ignored.
Transmitter Halt Control Input.
When TXHALT is asserted LOW, transmission of data is suspended and the
HOTLink TAXI transmits SYNC characters. When TXHALT is deasserted HIGH,
normal data processing proceeds.
If the Transmit FIFO is enabled (FIFOBYP is HIGH), the interface is allowed to
continue loading data into the Transmit FIFO while TXHALT is asserted.
Transmit FIFO Full Status Flag.
When the Transmit FIFO is enabled (FIFOBYP is HIGH) and its flags are driven
(CE is LOW), TXFULL is asserted when four or fewer characters can be written
to the HOTLink Transmit FIFO. If a Transmit FIFO reset has been initiated
(TXRST was sampled asserted for a minimum of seven TXCLK cycles),
TXFULL is asserted to enforce the full/unavailable status of the Transmit FIFO
during reset.
When the Transmit FIFO is bypassed (FIFOBYP is LOW), the TXFULL output
changes after the rising edge of REFCLK. TXFULL is asserted when the trans-
mitter is BUSY (not accepting a new data or command characters) and
deasserted when new characters can be accepted.
When the Transmit FIFO is bypassed and RANGESEL is HIGH or SPDSEL is
LOW, TXFULL toggles at the character rate to provide a character rate
reference control-indication since REFCLK is operating at twice of the data rate.
The asserted state of this output (HIGH or LOW) is determined by the state of
the EXTFIFO input. When EXTFIFO is LOW, TXFULL is active LOW. When
EXTFIFO is HIGH, TXFULL is active HIGH.
Signal Description
CY7C9689A
Page 5 of 51
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