CY7C9689A-AC Cypress Semiconductor Corp, CY7C9689A-AC Datasheet - Page 37

• Manufacturer Part Number: CY7C9689A-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AC

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
Receive
synchronous to the recovered bit-clock, which is divided by 10,
generate the output RXCLK clock. In this mode the RXRST
input is not interpreted and may be biased either HIGH or
LOW.
These modes are usually used for products that must meet
specific protocol requirements. New decoded characters are
provided at the RXDATA outputs once every rising edge of
RXCLK. If RXEMPTY is asserted LOW, the characters on the
RXCMD output register is a JK or LM sync character, and the
discard policy is set to non-0. Because the decoder is now
enabled, all received characters are checked for compliance
to the 4B/5B decoding rules.
Output Register Mapping
The RXDATA[11:0] output bus is mapped into a character
consisting of eight bits of data and four bits of command, or ten
bits of data and two bits of command. An accompanying
RXSC/D bit identifies the character as either command or
data.
The Violation (VLTN) output indicates a code violation has
occurred. When the VLTN output is asserted HIGH, this
indicates a transmission error is detected in the character at
the current transfer clock cycle.
Synchronous Undecoded
In this mode, both the Receive FIFO and the 5B/4B, 6B/5B
Decoder are bypassed, and data passes directly from the
Deserializer to the output register. The Deserializer operates
synchronous to the recovered bit-clock, which is divided by 10
to generate the output RXCLK clock. In this mode the RXRST
input is not interpreted and may be biased either HIGH or
LOW.
This mode is usually used for products containing external
decoders or descramblers that must meet specific protocol
requirements. New data is provided at the RXDATA outputs
once every rising edge of RXCLK. Received characters are
not checked for any specific coding requirements and no
decoding errors are reported.
Asynchronous Decoded
In Asynchronous Decoded mode, both the Receive FIFO and
the Decoder of the CY7C9689A are enabled. The deserializer
operates synchronous to the recovered bit-clock, which is
divided by 10 to generate the Receive FIFO write clock.
Characters are read from the Receive FIFO, using the external
RXCLK input, when addressed by CE and selected by RXEN.
In this mode the RXRST input is interpreted.
Output
Register.
The
Deserializer
operates
Asynchronous Decoded mode supports the same Output
Register mapping as the Synchronous Decoded mode.
Because both the Receive FIFO and Decoder are enabled, the
output FIFO may be read at any rate supported by the FIFO,
however, if the Receive FIFO ever indicates a full condition
(RXFULL is asserted), data may be lost.
Asynchronous Undecoded
In Asynchronous Undecoded modes, the Receive FIFO is
enabled. This means that all characters received from the
serial interface are written to the Receive FIFO before being
passed to the output register. The Deserializer operates
synchronous to the recovered bit-clock, which is divided by 10
(or 12) to generate the Receive FIFO write clock. Data is read
from the Receive FIFO, using the RXCLK input clock, when
addressed by CE and selected by RXEN.
These modes are usually used for products containing
external decoders or descramblers, that must meet specific
protocol requirements. New data may be read from the
Receive FIFO any time that the FIFO status flags indicate a
non-empty condition (RXEMPTY is deasserted). To ensure
that data is not lost, the Receive FIFO must be read faster than
data is loaded into the Receive FIFO.
If the receiver is to provide framed characters, it is necessary
for the transmit end to include JK or LM sync characters in the
data stream. This can be done by:
BIST Operation and Reporting
The CY7C9689ADX HOTLink Transceiver incorporates the
same Built-In Self-Test (BIST) capability. This link diagnostic
uses a Linear Feedback Shift Register (LFSR) to generate a
511-character
character-for-character, at the receiver.
BIST mode is intended to check the entire high-speed serial
link at full link-speed, without the use of specialized and
expensive test equipment. The complete sequence of
characters used in BIST are documented in
• operating the transmitter in encoded mode and writing JK
• operating the transmitter in pre-encoded mode and writing
• not enabling the transmitter when it is operated in
or LM characters into the data stream
the 10-bit value for an encoded JK (1100010001) or LM
(011000100011) character to the data stream
synchronous mode, or by allowing the transit FIFO to go
empty when it is operated in asynchronous mode.
repeating
sequence
CY7C9689A
that
Table
is
Page 37 of 51
4.
compared,
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