CY7C9689A-AC Cypress Semiconductor Corp, CY7C9689A-AC Datasheet - Page 45

• Manufacturer Part Number: CY7C9689A-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AC

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
FIFO Reset Sequence
On power-up, the Transmitter and Receiver FIFOs are cleared
automatically. If the usage of the FIFOs in specific operating
modes results in stale or unwanted data, this data can be
cleared by resetting the respective FIFO. Data in the Transmit
FIFO will empty automatically if it is enabled to read the FIFO
(assuming TXHALT is not LOW). Stale received data can be
“flushed” by reading it, or the Receive FIFO can be reset to
remove the unwanted data.
The Transmit and Receive FIFOs are reset when the
Tx_RstMatch or Rx_RstMatch condition remains present for
eight consecutive clock cycles. Any disruption of the reset
sequence prior to reaching the eight cycle count, either by
removal of CE or the respective TXRST or RXRST, or
assertion of the associated TXEN or RXEN, terminates the
sequence and does not reset the FIFO. Because CE must
remain asserted during the reset sequence, the addressed
FIFO flags remain driven during the entire sequence.
Transmit FIFO Reset Sequence
The Transmit FIFO reset sequence (see
when TXRST and CE are first sampled LOW by the rising edge
of TXCLK. Because a Tx_RstMatch condition is present, the
Transmit FIFO flags are asserted and can be used to track the
status of any Transmit FIFO reset in progress. Once the reset
sequence has reached its maximum count (eight TXCLK
cycles), the Transmit FIFO flags are asserted to indicate a
FULL condition (TXEMPTY is deasserted, and both TXHALF
and TXFULL are asserted). This indicates that the Transmit
Rx_RstMatch
RXEMPTY
Rx_Match
Figure 12. Receive FIFO Reset Address Match
RXRST
RXCLK
CE
[46]
[46]
Valid
Figure
Valid
15) is started
FIFO reset has been recognized by the Transmit Control State
Machine and that a reset has been started. However, if the
TXEN is asserted prior to or during the assertion and sampling
of TXRST, the reset sequence is inhibited until TXEN is
removed. Note: The FIFO FULL state forced by the reset
operation is different from a FULL state caused by normal
FIFO data writes. For normal FIFO write operations, when
FULL is first asserted, the Transmit FIFO must still accept up
to four additional writes of data. When a FULL state is asserted
due to a Transmit FIFO reset operation, the FIFO will not
accept any additional data.
The Transmit FIFO reset does not complete until the external
reset condition is removed. This can be removed by
deassertion of either TXRST or CE. If CE is deasserted (HIGH)
to remove the reset condition, the Transmit FIFO flag’s drivers
are disabled, and the Transmit FIFO must be addressed at a
later time to validate completion of the Transmit FIFO reset. If
TXRST is deasserted (HIGH) to remove the reset condition,
the Tx_RstMatch is changed to a Tx_Match, and the Transmit
FIFO status flags remain driven. The Transmit FIFO reset
operation is complete when the Transmit FIFO flags indicate
an EMPTY state (TXEMPTY is asserted and both TXHALF
and TXFULL are deasserted). A valid Transmit FIFO reset
sequence is shown in
Here the TXRST and CE are asserted (LOW) at the same
time. When these signals are both sampled LOW by TXCLK,
a Tx_RstMatch condition is present. With TXEN deasserted
(HIGH), the Transmit FIFO is not selected for data transfers.
This Tx_RstMatch condition must remain for eight TXCLK
cycles to initiate the Tx_FIFO_Reset. Following this the
TXFULL FIFO status flag is asserted to indicate that the
Transmit FIFO reset sequence has completed and that a
Transmit FIFO reset is in progress.
When the TXRST signal is deasserted (HIGH), CE remains
LOW to allow the FIFO status flags to be driven. This allows
the completion of the reset operation to be monitored. To allow
better multi-tasking on multi-PHY implementations, it is
possible to deassert CE (HIGH) as soon as the FULL state is
indicated. The FIFO reset operation will complete and the
EMPTY state (indicating completion of the reset operation)
can be detected during a separate polling operation.
For those links implemented with a single PHY, it is possible
to hardwire CE LOW and still perform normal accesses and
reset operations. This is shown in
implementation, a Transmit FIFO reset can never be initiated
with TXEN asserted at the same time as TXRST. Since CE is
always LOW, any assertion of TXEN causes the Transmit
FIFO to be selected, clearing the reset counter.
Figure
15.
Figure
CY7C9689A
. In a single-PHY
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