HBLXT9781HC.C4 Intel, HBLXT9781HC.C4 Datasheet - Page 67

• Manufacturer Part Number: HBLXT9781HC.C4
• Manufacturer: Intel

Specifications of HBLXT9781HC.C4

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
3.15:10
3.9:4
3.3:0
4.15
4.14
4.13
4.12
4.11
4.10
1. RO = Read Only
1. R/W = Read/Write
2. The default setting of bit 4.10 (PAUSE) is determined by pin 79.
3. Default settings for bits 4.5:8 are determined by LED?CFG pins as described in
I/G
a
1
0
Bit
RO = Read Only
Bit
Table 38. PHY Identification Register 2 (Address 3)
Figure 38. PHY Identifier Bit Mapping
Table 39. Auto-Negotiation Advertisement Register (Address 4)
b
2
0
0
15
3
0
c
Next Page
Reserved
Remote Fault
Reserved
Asymmetric
Pause
Pause
0
revision number
PHY ID number
Manufacturer’s
Manufacturer’s
00
model number
0
Name
0
Name
Organizationally Unique Identifier
PHY ID Register #1 (Address 2)
0
The Level One OUI is 00207B hex.
0
0
0
The Intel
1 = Port has ability to send multiple pages.
0 = Port has no ability to send multiple pages.
Ignore.
1 = Remote fault.
0 = No remote fault.
Ignore.
Pause operation defined in Clause 40 and 27
1 = Pause operation enabled for full-duplex links.
0 = Pause operation disabled.
0
0
The PHY identifier composed of bits 19 through 24 of the
OUI.
6 bits containing manufacturer’s part number.
4 bits containing manufacturer’s revision number.
Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781
0
0
0
0
20
1
0
1
2
0
0
Description
3
1
Description
18 19
0
1
r
B
15
s
0
1
7B
1
PHY ID Register #2 (Address 3)
1
7
1
Table 9 on page
24
10
0
x
X
9
5
Manufacturer’s
Model Number
X
X
Type
RO
29.
RO
RO
X
1
X
001010 (LXT9781)
X
000111 (LXT9761)
4
0
Type
R/W
R/W
R/W
R/W
R/W
RO
3
X
3
Revision
Default
Number
011110
XXXX
X
1
Default
X
Note 2
0
0
0
0
0
X
0
0
67