HBLXT9781HC.C4 Intel, HBLXT9781HC.C4 Datasheet - Page 25

• Manufacturer Part Number: HBLXT9781HC.C4
• Manufacturer: Intel

Specifications of HBLXT9781HC.C4

• Lead Free Status / RoHS Status: Not Compliant

2.2.3.2
2.3
2.3.1
Datasheet
Force Interrupt
1. Interrupt (Event) Status Register is cleared on read.
2. X = Any Interrupt capability
Event X Enable Reg
Event X Status Reg
Figure 9. Interrupt Logic
Per Event
. .
.
MII Interrupts
The LXT97x1 provides a single interrupt pin available to all ports. Interrupt logic is shown in
Figure
provides interrupt enable and mask functions and Register 19 provides interrupt status. Setting bit
18.1 = 1, enables a port to request interrupt via the MDINT pin. An active Low on this pin indicates
a status change on the LXT97x1. However, because it is a shared interrupt, it does not indicate
which port is requesting service.
Interrupts may be caused by any one of the following conditions:
Hardware Control Interface
The LXT97x1 provides a Hardware Control Interface for applications where the MDIO is not
desired. The Hardware Control Interface uses the three LED driver pins for each port.
Operating Requirements
Power Requirements
The LXT97x1 requires four power supply inputs: VCCD, VCCT, VCCR, and VCCIO. The digital
and analog circuits require 3.3 V supplies (VCCD, VCCT and VCCR). These inputs may be
supplied from a single source although decoupling is required to each respective ground.
An additional supply may be used for the RMII (VCCIO).
same power source used to supply the controller on the other side of the RMII interface. Refer to
Table 18 on page 53
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•
•
•
Auto-negotiation complete.
Speed status change.
Duplex status change.
Link status change.
9. The LXT97x1 also provides two dedicated interrupt registers for each port. Register 18
AND
Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781
for RMII I/O characteristics.
Interrupt Enable
OR
AND
Per port
VCCIO should be supplied from the
. . .
Port
Combine
Logic
Interrupt Pin
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