HBLXT9781HC.C4 Intel, HBLXT9781HC.C4 Datasheet - Page 17
![](/photos/31/31/313122/208pin_pqfp_sml.jpg)
HBLXT9781HC.C4
Manufacturer Part Number
HBLXT9781HC.C4
Description
Manufacturer
Intel
Datasheet
1.HBLXT9781HC.C4.pdf
(78 pages)
Specifications of HBLXT9781HC.C4
Lead Free Status / RoHS Status
Not Compliant
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Datasheet
1. Pin numbers apply to both the LXT9761 and the LXT9781.
2. Type Column Coding: I = Input, O = Output, A = Analog, IP = weak Internal Pull-up, ID = weak Internal pull-Down.
3. The LXT97x1 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
PQFP
Pin#
102
206
207
where X is the register number (0-32) and Y is the bit number (0-15).
Table 5. LXT97x1 Miscellaneous Signal Descriptions
76
77
79
82
83
97
96
95
94
93
1
9781 PBGA
Pin#
W10
W12
W16
W15
U10
V12
V15
V13
V14
V17
Y8
B4
A3
TxSLEW_0
TxSLEW_1
PAUSE
PWRDWN
RESET
ADD_4
ADD_3
ADD_2
ADD_1
ADD_0
RBIAS
QSTAT
QCLK
Symbol
Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781
Type
AI
O
I
I
I
I
I
I
I
I
I
I
2
Tx Output Slew Controls 0 and 1. These pins select the TX output
slew rate (rise and fall time) as follows:
TxSLEW_1
Pause. Sets the default value of bit 4.10 (PAUSE). When High, the
LXT97x1 advertises Pause capabilities on all ports during auto-
negotiation.
Power-Down. When High, forces the LXT97x1 into global power-down
mode. Refer to
Reset. This active Low input is OR’ed with the control register Reset bit
(0.15). When held Low, all outputs are forced to inactive state.
Address <4:0>. Sets base address. Each port adds its port number
(starting with 0) to this address to determine its PHY address.
Port 0 Address = Base + 0.
Port 1 Address = Base + 1.
Port 2 Address = Base + 2.
Port 3 Address = Base + 3.
Port 4 Address = Base + 4.
Port 5 Address = Base + 5.
Port 6 Address = Base + 6 (LXT9781 Only).
Port 7 Address = Base + 7 (LXT9781 Only).
Bias. This pin provides bias current for the internal circuitry. Must be tied
to ground through a 22.1 k
Quick Status. Provides continuous PHY status updates, without the
need for constant polling.
Quick Clock. Clock used for sending out QSTAT information. Maximum
frequency is 25 MHz.
0
0
1
1
“Power-Down Mode” on page 27
TxSLEW_0
0
1
0
1
Signal Description
1% resistor.
Slew Rate (Rise and Fall Time)
2.5 ns
3.1 ns
3.7 ns
4.3 ns
3
for more information.
17
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