HBLXT9781HC.C4 Intel, HBLXT9781HC.C4 Datasheet - Page 31

• Manufacturer Part Number: HBLXT9781HC.C4
• Manufacturer: Intel

Specifications of HBLXT9781HC.C4

• Lead Free Status / RoHS Status: Not Compliant

2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
Datasheet
Figure 13. Loopback Paths
Reference Clock
The LXT97x1 requires a 50 MHz reference clock (REFCLK). The LXT97x1 samples the RMII
input signals on the rising edge of REFCLK and drives RMII output signals on the falling edge.
Transmit Enable
TXENn must be asserted and de-asserted synchronously with REFCLK. The MAC must assert
TXENn the same time as the first nibble of preamble. TXENn must be de-asserted after the last bit
of the packet.
Carrier Sense & Data Valid
The LXT97x1 asserts CRS_DVn when it detects activity on the line. However, RXDn outputs
zeros until the received data is decoded and available for transfer to the controller.
Receive Error
Whenever the LXT97x1 receives an errored symbol from the network, it asserts RXERn. When it
detects a bad Start-of-Stream Delimiter (SSD) it drives a “10” jam pattern on the RXD pins to
indicate a false carrier event.
Loopback
A test loopback function is available for 100 Mbps RMII testing. Bits 0.8, 0.13 and 0.14 must be
set High for correct operation. When data is looped back, whatever the MAC transmits is looped
back in its entirety, including the preamble. In FX mode, the respective SIGDET pin must be
pulled High to enable loopback.
Out of Band Signalling
The LXT97x1 has the capability of encoding status information in the RXData stream during IPG.
Refer to the section on Monitoring Operations
LXT97x1
MII
Loopback
10T
Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781
Digital
Block
Loopback
100X
Analog
Block
(page
FX Driver
TX Driver
42) for details.
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