FWLXT9785BC Cortina Systems Inc, FWLXT9785BC Datasheet - Page 207

• Manufacturer Part Number: FWLXT9785BC
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9785BC

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 100
Cortina Systems
Trim Enable Register (Address 27, Hex 1B)
®
1. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
2. Default values for Register bits 27.11:10 are determined by the TxSLEW pins.
3. Default value for Register bit 27.9 is determined by the AMDIX_EN pin.
4. Default value for Register bit 27.8 is determined by the MDIX pin. BGA15 does not support the MDIX
5. R/W = Read/Write, R = Read Only, LH = Latching High – cleared when read.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
15:13
11:10
Bit
12
9
8
7
6
5
4
the pin(s) are latched at startup or hardware reset.
hardware configuration. The BGA15 default = 0.
Name
Reserved
Reserved
Per-Port
Rise Time
Control
AMDIX_EN
MDIX
Analog
Loopback
Reserved
Power_EN
Dis_EN
Description
Write as 0, ignore on Read
Write as 0, ignore on Read.
00 = 3.3 ns
01 = 3.6 ns
10 = 3.9 ns
11 = 4.2 ns
Note:
0 = Disable auto MDI/MDIX
1 = Enable auto MDI/MDIX
0 = MDI, transmit on pair A (TPFIN n /TPFIP n ) and receive on
1 = MDIX transmit on pair B (TPFON n /TPFOP n ) and receive
Note:
Note:
0 = Disable analog loopback
1 = Enable analog loopback (twisted-pair transmit outputs are
Note:
DTE Discovery Process Enable.
0 = Disable DTE discovery process
1 = Enable DTE discovery process
Restart auto-negotiation after writing to this bit to ensure
proper operation.
Write as 0, ignore on Read.
Power Enable (Requires Auto-Negotiation Enable
Register bit 0.12 = 1).
0 = Remote-Power DTE not discovered; process may not be
1 = Potential Remote-Power DTE discovered; indication to
pair B (TPFON n /TPFOP n )
on pair A (TPFIN n /TPFIP n )
active)
complete.
turn on power over the cable.
Values represent nominal load conditions.
Manual MDI/MDIX selection (This bit is ignored when
Register bit 27.9 = 1).
BGA15 does not support the MDIX hardware
configuration.
In fiber mode, SD for the port must be asserted.
7.0 Register Definitions
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
5
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LSHR
LSHR
LSHR
Default
N/A
0
0
0
0
0
1,2
1,3
1,4