FWLXT9785BC Cortina Systems Inc, FWLXT9785BC Datasheet - Page 146

• Manufacturer Part Number: FWLXT9785BC
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9785BC

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.10
Note:
4.10.1
4.10.2
4.10.3
Cortina Systems
The occurrence of a Far End Fault causes all transmission of data from the Reconciliation
Sublayer to stop and the Far End fault code to begin. The Far End Fault code consists of
84 ones’s followed by a single “0” and is repeated until the Far End Fault condition is
removed.
10 Mbps Operation
The LXT9785/LXT9785E operates as a standard 10BASE-T transceiver and supports all
the standard 10 Mbps functions. During 10BASE-T (10T) operation, the LXT9785/
LXT9785E transmits and receives Manchester-encoded data across the network link.
When the MAC is not actively transmitting data, the device sends out link pulses on the
line.
In 10T mode, the polynomial scrambler/descrambler is inactive. Manchester-encoded
signals received from the network are decoded by the LXT9785/LXT9785E and sent
across the MII to the MAC.
The LXT9785/LXT9785E does not support fiber connections at 10 Mbps.
Preamble Handling
The LXT9785/LXT9785E offers two options for preamble handling, which are selected by
Register bit 16.5. In 10BASE-T mode, when Register bit 16.5 = 0, the device strips the
preamble off the received packets. In RMII and the SMII modes, the CRS signal is
asserted based upon receive activity. In the SMII modes, Out-of-Band (OOB) signaling is
present until the SFD is output. The DV signal is initially asserted in the frame that the
SFD is output. In RMII mode, zeros are output after receive activity is detected until the
SFD is output. The packet is output following the SFD.
When Register bit 16.5 = 1 in 10BASE-T mode, the LXT9785/LXT9785E passes the
preamble through the RMII and the SMII interfaces. In RMII and the SMII modes, the CRS
signal is asserted based upon receive activity. In the SMII modes, OOB signaling is
continued until preamble is available from the receive FIFO. After the preamble, the SFD
is output with the initial assertion of the DV signal. The RMII interface outputs zeros after
receive activity is detected until preamble is available from the FIFO. The number of zero
nibbles output before preamble is based upon the FIFO initial fill settings (Register bits
18.15:14). The preamble is followed by the SFD and the packet body. Register bit 16.5
has no effect in 100 Mbps operation.
Dribble Bits
The LXT9785/LXT9785E device handles dribble bits in all modes. If one through four
dribble bits are received, the nibble is passed across the RMII. If five through seven
dribble bits are received, the second nibble is not sent onto the RMII bus.
Link Test
The LXT9785/LXT9785E always transmits link pulses in 10T mode. When enabled, the
link test function monitors the connection for link pulses. Once link pulses are detected,
data transmission is enabled and remains enabled as long as either the link pulses or data
transmission continue. If link pulses stop, the data transmission is disabled.
®
• When Register bit 16.2 = 0, the LXT9785/LXT9785E does not transmit far end fault
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
code. It continues to transmit idle code and may or may not drop link depending on
the setting for Register bit 16.14.
4.10 10 Mbps Operation
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