FWLXT9785BC Cortina Systems Inc, FWLXT9785BC Datasheet - Page 113

• Manufacturer Part Number: FWLXT9785BC
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9785BC

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.0
4.1
Note:
4.1.1
Cortina Systems
Functional Description
Introduction
The Cortina Systems
transceiver that supports 10 Mbps and 100 Mbps networks, complying with all applicable
requirements of IEEE 802.3 standards. The device incorporates a Serial Media
Independent Interface (SMII), Source Synchronous-Serial Media Independent Interface
(SS-SMII), and a Reduced Serial Independent Interface (RMII) to enable each individual
network port to interface with multiple 10/100 MACs. Each port directly drives either a
100BASE-TX line or a 10BASE-T line. The LXT9785/LXT9785E also supports 100BASE-
FX operation via an LVPECL interface. The device has a 241-ball BGA, a 208-pin QFP, or
a 196-ball BGA package.
The 196-ball BGA package (BGA15) is a reduced feature-set product designated as the
LXT9785MBC. The BGA15 package does not support the following features:
Unless otherwise noted, all information in this document applies to the LXT9785 and
LXT9785E.
OSP™ Architecture
The LXT9785/LXT9785E incorporates high-efficiency Optimal Signal Processing™
design techniques, combining the best properties of digital and analog signal processing
to produce a truly optimal device.
The receiver utilizes decision feedback equalization to increase noise and cross-talk
immunity by as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal
processing techniques in the receive equalizer avoids the quantization noise and
calculation truncation errors found in traditional DSP-based receivers (typically complex
DSP engines with A/D converters). The result is improved receiver noise and cross-talk
performance.
The OSP architecture also requires substantially less computational logic than traditional
DSP-based designs. The result is lower power consumption and reduced logic switching
noise generated by DSP engines clocked at speeds up to 125 MHz. The logic switching
noise can be a considerable source of EMI when generated from the device’s power
supplies.
The OSP-based LXT9785/LXT9785E provides improved data recovery, EMI performance
and power consumption.
®
• RMII
• Fiber
• Sectionalization
• Hardware control pins:
• Extended temperature
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
— PAUSE
— MDIX
— MDDIS
— PWRDWN
— Lower three PHY address (out of five PHY address bits)
®
LXT9785/LXT9785E is an 8-port Fast Ethernet 10/100 PHY
4.0 Functional Description
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