FWLXT9785BC Cortina Systems Inc, FWLXT9785BC Datasheet - Page 159

• Manufacturer Part Number: FWLXT9785BC
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9785BC

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.14
4.14.1
4.14.2
Cortina Systems
Link Hold-Off Overview
The PHY link is established as soon as the system platform powers-up. In many cases,
the system platform is not capable of supporting network operation until configuration
firmware is loaded. It is desirable in such cases to prevent the PHY from establishing a
link until the system platform is fully configured and ready for network operation. Link
Hold-Off was incorporated into the LXT9785/LXT9785E device to satisfy these
requirements. Enabling Link Hold-Off disables the PHY Link capability until the system
platform is fully capable of supporting network operation. The feature is enabled by
hardware control at power-up or software control during normal operation.
Features
Link Hold-Off prevents the LXT9785/LXT9785E from establishing a link by disabling the
analog transmit and receive capability. The digital capabilities of the PHY are unaffected
including register access and LED operation. Link Hold-Off can be enabled by an external
hardware pin for all ports or by software register access for individual ports. When Link
Hold-Off is enabled, the transmitter and receiver on the selected ports are forced into
software power-down mode (see
signal activity from establishing a link and passing packets through the PHY.
The hardware enabled Link Hold-Off is controlled by the LINKHOLD pin. Internal pull-
down resistors hold the pin in the inactive state. Connecting a 5k pull-up resistor to the pin
enables the feature at power-up reset or external hardware pin Reset. Once a PHY port is
programmed as desired, clearing Register bit 0.11 will re-enable that port. Each port must
be individually re-enabled.
When a port is software reset, by setting Register 0.15, the state of the hardware
configuration pin captured by the last hardware or power-up reset determines the default
register values for the specific function for that port. Link Hold-Off, once enabled by
hardware configuration, is re-enabled on a port by issuing a software reset for that port. It
is not necessary to reset the entire PHY or switch system to re-enable Link Hold-Off.
Link Hold-Off software control is enabled or disabled on individual ports by respectively
setting or clearing Register bit 0.11, the power-down bit, during normal operation. It is not
required to have previously enabled Link Hold-Off by hardware configuration.
Link Hold-Off is disabled if the external pin MDDIS is active. The MDDIS pin disables the
MDIO interface required to re-enable normal transmit and receive link operation. MDDIS
is intended to disable the MDIO management interface for unmanaged applications.
Internal loopback circuitry is unaffected in Link Hold-Off mode.
Operation
Link Hold-Off is implemented in one of the following two ways:
Link Hold-Off use by an external hardware pin is as follows:
®
1. Pull the LINKHOLD pin High with a pull-up resistor (approximately 5 k Ohms).
2. Power up the system or drive the reset pin active.
3. All ports are link disabled.
4. Program all ports to the desired configuration.
• Using a hardware pin at power-up or hardware reset
• Using software control through the MII Management (MDC/MDIO) interface.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Section 4.5.3, Power-Down Mode, on page
4.14 Link Hold-Off Overview
124) to block
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