IDTICS1893CFLFT IDT, Integrated Device Technology Inc, IDTICS1893CFLFT Datasheet - Page 112
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IDTICS1893CFLFT
Manufacturer Part Number
IDTICS1893CFLFT
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDTICS1893CFLFT.pdf
(127 pages)
Specifications of IDTICS1893CFLFT
Lead Free Status / RoHS Status
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9.5.10 100M / MII Media Independent Interface: Transmit Latency
ICS1893CF, Rev. J, 08/11/09
TXEN
TXCLK
TXD
TP_TX
Table 9-17
periods consist of timings of signals on the following pins:
•
•
•
•
Figure 9-11
Table 9-17. MII / 100M Stream Interface Transmit Latency
† The IEEE maximum is 18 bit times.
Figure 9-11. MII / 100M Stream Interface Transmit Latency Timing Diagram
Period
Time
†
unscrambled.
TXEN
TXCLK
TXD (that is, TXD[3:0])
TP_TX (that is, TP_TXP and TP_TXN)
t1
Shown
†
ICS1893CF Data Sheet - Release
TXEN Sampled to MDI Output of First
Bit of /J/ †
lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time
shows the timing diagram for the time periods.
Preamble /J/
Parameter
Copyright © 2009, Integrated Device Technology, Inc.
Preamble /K/
All rights reserved.
t1
112
MII mode
Conditions
Chapter 9 DC and AC Operating Conditions
Min.
–
Typ. Max.
2.8
3
August, 2009
Bit times
Units
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