LAN83C185-JT Standard Microsystems (SMSC), LAN83C185-JT Datasheet - Page 41

• Manufacturer Part Number: LAN83C185-JT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN83C185-JT

• Lead Free Status / RoHS Status: Compliant

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185
30.15:8
30.7:0
31.15
31.14
31.13
31.12
31.11:10
31.9:7
31.6
31.5
29.6
29.5
29.4
29.3
29.2
29.1
29.0
ADDRESS
ADDRESS
ADDRESS
Reserved
Reserved
Special
Autodone
Reserved
GPO[2:0]
Enable 4B5B
Reserved
INT6
INT5
INT4
INT3
INT2
INT1
Reserved
Reserved
Mask Bits
NAME
NAME
NAME
Table 5.50 Register 29 - Interrupt Source Flags (continued)
Table 5.52 Register 31 - PHY Special Control/Status
Do not write to this register. Ignore on read.
Auto-negotiation done indication:
General Purpose Output connected to signals
Must be set to 0
0 = Auto-negotiation is not done or disabled (or not
1 = Auto-negotiation is done
GPO[2:0]
0 = Bypass encoder/decoder.
1 = enable 4B5B encoding/decoding.
MAC Interface must be configured in MII mode.
Write as 0, ignore on Read.
Write as 0; ignore on read.
1 = interrupt source is enabled
0 = interrupt source is masked
1 = Auto-Negotiation complete
0 = not source of interrupt
1 = Remote Fault Detected
0 = not source of interrupt
1 = Link Down (link status negated)
0 = not source of interrupt
1 = Auto-Negotiation LP Acknowledge
0 = not source of interrupt
1 = Parallel Detection Fault
0 = not source of interrupt
1 = Auto-Negotiation Page Received
0 = not source of interrupt
Table 5.51 Register 30 - Interrupt Mask
active)
DATASHEET
DESCRIPTION
DESCRIPTION
DESCRIPTION
41
RO/
LH
RO/
LH
RO/
LH
RO/
LH
RO/
LH
RO/
LH
RO/
LH
RO
RW
MODE
RW
RW
RO
RW
RW
RW
RW
MODE
MODE
Revision 0.8 (06-12-08)
DEFAULT
0
0
0
0
0
0
0
DEFAULT
0
0
0
0
DEFAULT
0
0
0
0
1