LAN83C185-JT Standard Microsystems (SMSC), LAN83C185-JT Datasheet - Page 38

• Manufacturer Part Number: LAN83C185-JT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN83C185-JT

• Lead Free Status / RoHS Status: Compliant

Revision 0.8 (06-12-08)
18.15:14
18.13
18.12
18.11
18.10
18.9
18.8
18.7:5
17.8
17.7:5
17.4
17.3
17.2
17.1
17.0
ADDRESS
ADDRESS
MIIMODE
CLKSELFREQ
DSPBP
SQBP
PLLBP
ADCBP
MODE
FASTEST
Reserved
Reserved
PHYADBP
Force
Good Link Status
ENERGYON
Reserved
Reserved
NAME
NAME
Table 5.42 Register 17 - Mode Control/Status (continued)
MII Mode: set the mode of the MII:
0 – MII interface.
1 – Reserved
Clock In Selected Frequency. Set the requested input
clock frequency. This bit drives signal that goes to
external logic of the Phy and select the desired
frequency of the input clock:
0 – the clock frequency is 25MHz
1 – Reserved
DSP Bypass mode. Used only in special lab tests.
SQUELCH Bypass mode.
PLL Bypass mode.
ADC Bypass mode.
PHY Mode of operation. Refer to
"Mode Bus – MODE[2:0]," on page 46
details.
Auto-Negotiation Test Mode
0 = normal operation
1 = activates test mode
Write as 0, ignore on read.
Reserved
Must be left at 0
1 = PHY disregards PHY address in SMI access
0 = normal operation;
1 = force 100TX- link active;
Note:
ENERGYON – indicates whether energy is detected
on the line (see
Power-Down," on page
energy is detected within 256ms. Reset to “1” by
hardware reset, unaffected by SW reset.
Write as “0”. Ignore on read.
Table 5.43 Register 18 - Special Modes
write.
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
This bit should be set only during lab testing
DATASHEET
Section 5.4.5.2, "Energy Detect
DESCRIPTION
DESCRIPTION
38
43); it goes to “0” if no valid
Section 5.4.9.2,
for more
RW
RW
RW
RW
RO
RW
RW,
NASR
RO,
NASR
RW,
NASR
RW,
NASR
RW,
NASR
RW,
NASR
RW,
NASR
RW,
NASR
MODE
MODE
SMSC LAN83C185
DEFAULT
0
0
0
0
1
0
DEFAULT
0
0
Datasheet