LAN83C185-JT Standard Microsystems (SMSC), LAN83C185-JT Datasheet - Page 16

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LAN83C185-JT

Manufacturer Part Number
LAN83C185-JT
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

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Chapter 4 Architecture Details
Revision 0.8 (06-12-08)
4.1
4.2
4.2.1
4.2.2
Top Level Functional Architecture
100Base-TX Transmit
Functionally, the PHY can be divided into the following sections:
The data path of the 100Base-TX is shown in
100M Transmit Data across the MII
The MAC controller drives the transmit data onto the TXD bus and asserts TX_EN to indicate valid
data. The data is latched by the PHY’s MII block on the rising edge of TX_CLK. The data is in the
form of 4-bit wide 25MHz data.
4B/5B Encoding
The transmit data passes from the MII block to the 4B/5B encoder. This block encodes the data from
4-bit nibbles to 5-bit symbols (known as “code-groups”) according to
is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for
control information or are not valid.
The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles,
0 through F. The remaining code-groups are given letter designations with slashes on either side. For
example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc.
MAC
100Base-TX transmit and receive
10Base-T transmit and receive
MII interface to the controller
Auto-negotiation to automatically determine the best speed and duplex possible
Management Control to read status registers and write control registers
Converter
NRZI
RJ45
MII 25 MHz by 4 bits
TX_CLK
(for MII)
NRZI
MLT-3
Converter
Figure 4.1 100Base-TX Data Path
MLT-3
100M
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
PLL
CAT-5
DATASHEET
125 Mbps Serial
MII
MLT-3
MLT-3
16
by 4 bits
25MHz
Driver
Figure
Tx
4.1. Each major block is explained below.
Encoder
4B/5B
MLT-3
Magnetics
25MHz by
5 bits
Table
4.1. Each 4-bit data-nibble
Scrambler
and PISO
SMSC LAN83C185
Datasheet

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