SI3011-F-FSR Silicon Laboratories Inc, SI3011-F-FSR Datasheet - Page 90

• Manufacturer Part Number: SI3011-F-FSR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3011-F-FSR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Si3050 + Si3011
Register 59. RX Gain Control 1
Reset settings = xxxx_xxxx
90
Name
7:3
Bit
Type
2
1
0
Bit
Reserved Always write these bits to zero.
Reserved Always write this bit to zero.
Name
GCE
RG1
D7
0
Receive Gain 1.
This bit enables receive path gain adjustment.
0 = No gain applied to hybrid, full scale RX on line = 0 dBm.
1 = 1 dB of gain applied to hybrid, full scale RX on line = –1 dBm.
Guarded Clear Enable.
This bit (in conjunction with the R2 bit set to 1) enables the Si3050 to meet BT’s Guarded
Clear Spec (B5 6450, Part 1: 1993, Section 15.4.3.3). With these bits set, the DAA will draw
approximately 2.5 mA of current from the line while on-hook.
0 = Default, DAA does not draw loop current.
1 = Guarded Clear enabled, DAA draws 2.5 mA while on-hook to meet Guarded Clear
requirement.
D6
0
D5
0
Rev. 1.11
D4
0
Function
D3
0
RG1
R/W
D2
GCE
R/W
D1
D0
0