SI3011-F-FSR Silicon Laboratories Inc, SI3011-F-FSR Datasheet - Page 55

• Manufacturer Part Number: SI3011-F-FSR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3011-F-FSR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Register 1. Control 1
Reset settings = 0000_0000
Bit
5:4
7
6
3
2
1
0
Name
Type
Bit
PWMM[1:0] Pulse Width Modulation Mode.
Reserved Read returns zero.
Reserved Read returns zero.
Reserved Read returns zero.
PWME
Name
IDL
SR
R/W
SR
D7
Software Reset.
0 = Enables the DAA for normal operation.
1 = Sets all registers to their reset value.
Note: Bit automatically clears after being set.
Used to select the type of signal output on the call progress AOUT pin.
00 = PWM output is clocked at 16.384 MHz as a delta-sigma data stream. A local density of
1s and 0s tracks the combined transmit and receive signals. Use this setting with the optional
call progress circuit shown in Figure 18 on page 19.
01 = Balanced conventional PWM output signal has high and low portions of the modulated
pulse that are centered on the 16 kHz sample clock.
10 = Conventional PWM output signal returns to logic 0 at regular 32 kHz intervals and rises
at a time in the 32 kHz period proportional to its instantaneous amplitude.
11 = Reserved.
Pulse Width Modulation Enable.
0 = Pulse width modulation mode disabled (AOUT).
1 = Enable pulse width modulation mode for the call progress analog output (AOUT). This
mode sums the transmit and receive audio paths and presents this as a CMOS digital-level
output of PWM data. The circuit in Figure 18 on page 19 should be used.
Isolation Digital Loopback.
0 = Digital loopback across the isolation barrier is disabled.
1 = Enables digital loopback mode across the isolation barrier. The line-side device must be
enabled and off-hook prior to setting this mode. The data path includes the TX and RX filters.
D6
D5
PWMM[1:0]
R/W
Rev. 1.11
D4
Function
PWME
R/W
D3
Si3050 + Si3011
D2
R/W
IDL
D1
D0
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