MCZ33780EG Freescale, MCZ33780EG Datasheet - Page 24

• Manufacturer Part Number: MCZ33780EG
• Manufacturer: Freescale

Specifications of MCZ33780EG

• Operating Supply Voltage (typ): 5/12/15/18/24V
• Operating Supply Voltage (min): 4.75/9V
• Operating Supply Voltage (max): 5.25/25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Compliant

FIFO push operations or transfer abort actions. State
transitions in this state machine are synchronous with rising
edges of the SPI clock (SCLK). The initial state, SPI_IDLE, is
entered asynchronously whenever internal reset becomes
active or the SPI chip select (
entry to the idle state, the SPI_WRITE signal is deactivated
and the SPI bit counter is set to 7 (it will count down as bits
are received).
a command byte and the first bit indicates a write or read
command. The SPI_WRITE signal takes on the value of this
first bit, and the state machine enters the SPI_CMD_XFER
state, where the remaining bits of the command byte are
received. The last five bits of the command set the initial
value of the register pointer. After the command byte is
complete, the state machine advances to the SPI_BURST
transfers. State transfers in this state machine are
synchronous with positive edges on the scaled DBUS 1/3rd
bit clock and the initial state is WAIT_FRAME_DLY. Initial
24
33780
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure
When the
Figure 21
20, describes how SPI transfers lead to transmit
CS
describes what happens during DBUS serial
ASYNCHRONOUS RESET/
ACTION(S);
goes low (active), the first SPI transfer will be
RSTB ACTIVE or CSB INACTIVE/
SPI_WRITE = 0;
SPI_BIT_PTR = 7;
LAST_SPI_BIT/
CS
if SPI_WRITE & REG_PTR = CTRL or POLY or SEED or LENGTH or SSCTRL then ABORT;
if SPI_WRITE & REG_PTR = DATA_L then X_FIFO_PUSH;
if R_FIFO_NOT_EMPTY & REG_PTR = DATA_L then R_FIFO_POP;
SPI_BIT_PTR = 7;
REG_PTR = REG_PTR +1 (rolls over to 0 after 21);
) input is de-asserted. Upon
Figure 20. State Diagram of SPI Transfer
Figure 19. State Diagram Notation
SPI_CMD_XFER
STATE_1
SPI_BURST
IDLE
SPI_IDLE
LAST_SPI_BIT/
CSB ACTIVE/
SPI_BIT_PTR = 7;
INIT_REG_PTR FROM CMD BITS[4:0]
state, which remains active until
MC33780 is reset).
from, or written-to-and-read-from, MC33780 registers. If the
control register (or CRC polynomial, CRC seed, CRC length,
or spread spectrum control) is written, an ABORT request is
generated that will immediately stop any DBUS transfer that
was in progress (refer to the DBUS transfer state diagram). If
the DATA register low byte is written, a transmit FIFO push
operation is generated (see transmit FIFO state diagram). If
the DATA register low byte is accessed (read or written) and
there is at least one entry in the receive FIFO, a receive FIFO
pop operation is generated.
and an X_FIFO_POP, the R_FIFO_PUSH is performed first
to avoid the possibility of the transmit FIFO from getting
ahead of the receive FIFO.
entry into this state is caused by a reset, abort, or by enable
becoming inactive. These conditions cause an asynchronous
entry into this state. The exit to the next state,
WAIT_SIG_DLY_0, needs to be synchronous.
In the SPI_BURST state, new SPI characters are read-
When a DBUS transfer results in both an R_FIFO_PUSH
SPI_WRITE= MOSI;
SYNCHRONOUS CONDITIONS/
ACTION(S);
~LAST_SPI_BIT/
~LAST_SPI_BIT/
SPI_BIT_PTR = SPI_BIT_PTR-1;
SPI_BIT_PTR = SPI_BIT_PTR-1;
STATE TRANSITIONS OCCUR
ON POS EDGE OF XXX CLK
STATE TRANSITIONS OCCUR
ON POS EDGE OF SCLK
Analog Integrated Circuit Device Data
CS
Freescale Semiconductor
goes high (or the