GD82559ER S L3DG Intel, GD82559ER S L3DG Datasheet - Page 9

• Manufacturer Part Number: GD82559ER S L3DG
• Manufacturer: Intel

Specifications of GD82559ER S L3DG

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

2.
2.1
Datasheet
Interface
PCI
GD82559ER Architectural Overview
Figure 1
parallel subsystem, a FIFO subsystem, the 10/100 Mbps Carrier-Sense Multiple Access with
Collision Detect (CSMA/CD) unit, and the 10/100 Mbps physical layer (PHY) unit.
Parallel Subsystem Overview
The parallel subsystem is broken down into several functional blocks: a PCI bus master interface, a
micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/
Flash/EEPROM interface. The parallel subsystem also interfaces to the FIFO subsystem, passing
data (such as transmit, receive, and configuration data) and command and status parameters
between these two blocks.
The PCI bus master interface provides a complete glueless interface to a PCI bus and is compliant
with the PCI Bus Specification, Revision 2.2. The 82559ER provides 32 bits of addressing and
data, as well as the complete control interface to operate on a PCI bus. As a PCI target, it follows
the PCI configuration format which allows all accesses to the 82559ER to be automatically
mapped into free memory and I/O space upon initialization of a PCI system. For processing of
transmit and receive frames, the 82559ER operates as a master on the PCI bus, initiating zero wait
state transfers for accessing these data parameters.
The 82559ER Control/Status Register Block is part of the PCI target element. The Control/Status
Register block consists of the following 82559ER internal control registers: System Control Block
(SCB), PORT, Flash Control, EEPROM Control, and Management Data Interface (MDI) Control.
The micromachine is an embedded processing unit contained in the 82559ER. The micromachine
accesses the 82559ER microcode ROM working its way through the opcodes (or instructions)
contained in the ROM to perform its functions. Parameters accessed from memory such as pointers
to data buffers are also used by the micromachine during the processing of transmit or receive
frames by the 82559ER. A typical micromachine function is to transfer a data buffer pointer field
to the 82559ER DMA unit for direct access to the data buffer. The micromachine is divided into
two units, Receive Unit and Command Unit which includes transmit functions. These two units
is a high level block diagram of the 82559ER. It is divided into four main subsystems: a
Data Interface Unit
Addressing Unit -
Four Channel
Interface Unit
PCI Bus
(BIU)
(DIU)
DMA
Flash/EEPROM
PCI Target and
Local Memory
Interface
Interface
Figure 1. 82559ER Block Diagram
machine
Ported
Micro-
FIFO
Dual
FIFO Control
Rx FIFO
3 Kbyte
Tx FIFO
3 Kbyte
Networking Silicon — GD82559ER
10/100 Mbps
CSMA/CD
100BASE-TX/
10BASE-T
PHY
Interface
T P E
3