GD82559ER S L3DG Intel, GD82559ER S L3DG Datasheet
GD82559ER S L3DG
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GD82559ER S L3DG Summary of contents
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GD82559ER Fast Ethernet** PCI Controller Networking Silicon Product Features Optimum Integration for Lowest Cost Solution — Integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY — Glueless 32-bit PCI master interface — 128 Kbyte Flash interface 2 — Thin BGA 15mm ...
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... Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...
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INTRODUCTION ............................................................................................................................. 1 1.1 GD82559ER Overview ....................................................................................................... 1 1.2 Suggested Reading ............................................................................................................ 1 2. GD82559ER ARCHITECTURAL OVERVIEW ................................................................................ 3 2.1 Parallel Subsystem Overview ............................................................................................. 3 2.2 FIFO Subsystem Overview.................................................................................................4 2.3 10/100 Mbps Serial CSMA/CD Unit Overview.................................................................... 5 2.4 10/100 ...
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GD82559ER — Networking Silicon 6.1.2 100BASE-TX Transmit Blocks ......................................................................... 37 6.1.3 100BASE-TX Receive Blocks .......................................................................... 40 6.1.4 100BASE-TX Collision Detection ..................................................................... 41 6.1.5 100BASE-TX Link Integrity and Auto-Negotiation Solution.............................. 41 6.1.6 Auto 10/100 Mbps Speed Selection ................................................................. 41 6.2 10BASE-T ...
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Flow Control Register .......................................................................................60 8.1.11 Power Management Driver Register ................................................................60 8.1.12 General Control Register..................................................................................61 8.1.13 General Status Register ...................................................................................61 8.2 Statistical Counters...........................................................................................................62 9. PHY UNIT REGISTERS ................................................................................................................65 9.1 MDI Registers 0 - 7...........................................................................................................65 9.1.1 Register 0: Control Register Bit ...
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GD82559ER — Networking Silicon vi Datasheet ...
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... Introduction 1.1 GD82559ER Overview The 82559ER is part of Intel's second generation family of fully integrated 10BASE-T/100BASE- TX LAN solutions. The 82559ER consists of both the Media Access Controller (MAC) and the physical layer (PHY) combined into a single component solution. 82559 family members build on the basic functionality of the 82558 and contain power management enhancements. ...
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GD82559ER — Networking Silicon 2 Datasheet ...
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GD82559ER Architectural Overview Figure high level block diagram of the 82559ER divided into four main subsystems: a parallel subsystem, a FIFO subsystem, the 10/100 Mbps Carrier-Sense Multiple Access with Collision Detect (CSMA/CD) unit, and ...
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GD82559ER — Networking Silicon operate independently. Control is switched between the two units according to the microcode instruction flow. The independence of the Receive and Command units in the micromachine allows the 82559ER to interleave commands and receive incoming frames, ...
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Mbps Serial CSMA/CD Unit Overview The CSMA/CD unit of the 82559ER allows connected to either 100 Mbps Ethernet network. The CSMA/CD unit performs all of the functions of the 802.3 protocol such ...
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GD82559ER — Networking Silicon 6 Datasheet ...
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Signal Descriptions 3.1 Signal Type Definitions Type IN Input OUT Output T/S Tri-State S/T/S Sustained Tri-State O/D Open Drain A/I Analog Input A/O Analog Output B Bias 3.2 PCI Bus Interface Signals 3.2.1 Address and Data Signals Symbol AD[31:0] ...
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GD82559ER — Networking Silicon 3.2.2 Interface Control Signals Symbol FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# REQ# GNT# INTA# SERR# PERR# 8 Type Name and Function Cycle Frame. The cycle frame signal is driven by the current master to indicate the ...
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System and Power Management Signals Symbol CLK CLKRUN# RST# PME# ISOLATE# ALTRST# VIO 3.3 Local Memory Interface Signals Symbol FLD[7:0] FLA[16]/ CLK25 FLA[15]/ EESK FLA[14]/ EEDO Datasheet Type Name and Function Clock. The Clock signal provides the timing for ...
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GD82559ER — Networking Silicon Symbol FLA[13]/ EEDI FLA[12:8] FLA[7]/ CLKENB FLA[6:2] FLA[1]/ AUXPWR FLA[0] EECS FLCS# FLOE# FLWE# 3.4 Testability Port Signals Symbol TEST TCK TI TEXEC TO 10 Type Name and Function Flash Address[13]/EEPROM Data Input. During Flash accesses, ...
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PHY Signals Symbol X1 X2 TDP TDN RDP RDN ACTLED# LILED# SPEEDLED# RBIAS100 RBIAS10 VREF NOTE: 619 and 549 should be fine tuned for various designs. Datasheet Type Name and Function Crystal Input One. X1 and X2 can be ...
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GD82559ER — Networking Silicon 12 Datasheet ...
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GD82559ER Media Access Control Functional Description 4.1 82559ER Initialization The 82559ER has four sources for initialization. They are listed according to their precedence: 1. ALTRST# Signal 2. PCI RST# Signal 3. Software Reset (Software Command) 4. Selective Reset (Software ...
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GD82559ER — Networking Silicon 4.2 PCI Interface 4.2.1 82559ER Bus Operations After configuration, the 82559ER is ready for normal operation Fast Ethernet controller, the role of the 82559ER is to access transmitted data or deposit received data. In ...
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The figures below show CSR zero wait-state I/O read and write cycles. In the case of accessing the Control/Status Registers, the CPU is the initiator and the 82559ER is the target of the transaction. Read Accesses: The CPU, as the ...
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GD82559ER — Networking Silicon controls the TRDY# signal and asserts it from the data access. The 82559ER allows the CPU to issue only one I/O write cycle to the Control/Status Registers, generating a disconnect by asserting the STOP# signal. This ...
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CLK FRAME# AD C/BE# IRDY# TRDY# DEVSEL# STOP# Write Accesses: The CPU, as the initiator, drives the address lines byte enable lines C/BE#[3:0] and 82559ER with valid data immediately after asserting signal and de-asserts it for a certain number of ...
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GD82559ER — Networking Silicon Note: The 82559ER is considered the target in the above diagram; thus, TRDY# is not asserted. 4.2.1.1.4 Error Handling Data Parity Errors: The 82559ER checks for data parity errors while it is the target of the ...
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For bus master cycles, the 82559ER is the initiator and the host main memory (or the PCI host bridge, depending on the configuration of the system) is the target. CLK FRAME# AD ...
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GD82559ER — Networking Silicon Byte Count value indicates the maximum number of transmit DMA PCI cycles that will be completed after an 82559ER internal arbitration. (Details on the Configure command are described in the Software Developer’s Manual.) The 82559ER, as ...
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Minimum transfer of one cache line 2. Active byte enable bits (or BE#[3:0] are all low) during MWI access 3. The 82559ER may cross the cache line boundary only if it intends to transfer the next cache line too. ...
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GD82559ER — Networking Silicon • This feature is not recommended for use in non-cache line oriented systems since it may cause shorter bursts and lower performance. • This feature should be used only when the CLS register in PCI Configuration ...
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Power States The 82559ER’s power management register implements all four power states as defined in the Power Management Network Device Class Reference Specification, Revision 1.0. The four states, D0 through D3, vary from maximum power consumption ...
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GD82559ER — Networking Silicon 4.2.4.4 D3 Power State In the D3 power state, the 82559ER has the same capabilities and consumes the same amount of power as it does in the D2 state. However, it enables the PCI system to ...
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Power State D0u D0a (with power) Dx (x>0 without PME#) 4.2.4.6 Auxiliary Power Signal The 82559ER senses whether it is connected to the PCI power supply auxiliary power supply (V ) via the ...
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GD82559ER — Networking Silicon In a LAN on Motherboard solution, the PCI power good signal is supplied by the system. In network adapter implementations, the PCI power good signal can be either generated locally using an external analog device, or ...
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ISOLATE# trailing edge The internal initialization signal resets the PCI Configuration Space, MAC configuration, and memory structure. The behavior of the PCI RST# signal and the internal 82559ER initialization signal are shown in the figure below. PCI RST# Internal ...
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GD82559ER — Networking Silicon 4.2.5.2 Link Status Change Event The 82559ER link status indication circuit is capable of issuing a PME on a link status change from a valid link to an invalid link condition or vice versa. The 82559ER ...
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All accesses, either read or write, are preceded by a command instruction to the device. The address field is six bits for a 64 register EEPROM or eight bits for a 256 register EEPROM. The end of the address field ...
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GD82559ER — Networking Silicon Note that word 0Ah contains several configuration bits. Bits from word 0Ah, FBh through FEh, and certain bits from word 0Dh are described as follows: Word Bits 5:14 Signature 13 Reserved 12 Reserved 11 Boot Disable ...
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Full Duplex When operating in full duplex mode the 82559ER can transmit and receive frames simultaneously. Transmission starts regardless of the state of the internal receive path. Reception starts when the internal PHY detects a valid frame on the ...
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GD82559ER — Networking Silicon 4.6 Media Independent Interface (MII) Management Interface The MII management interface allows the CPU to control the PHY unit via a control register in the 82559ER. This allows the software driver to place the PHY in ...
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GD82559ER Test Port Functionality 5.1 Introduction The 82559ER’s NAND-Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing. The port pro- ...
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GD82559ER — Networking Silicon 5.5 TriState This command set all 82559ER Input and Output pins into a TRI-state (HIGH-Z) mode, all internal pull-ups and pull-downs are disabled. This mode is entered by setting the following Test Pin Com- binations: TEST ...
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Chain Order NAND-Tree Output Datasheet Networking Silicon — GD82559ER Table 2. Nand ...
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GD82559ER — Networking Silicon 36 Datasheet ...
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GD82559ER Physical Layer Functional Description 6.1 100BASE-TX PHY Unit 6.1.1 100BASE-TX Transmit Clock Generation A 25 MHz crystal MHz oscillator is used to drive the PHY unit’s X1 and X2 pins. The PHY unit derives its ...
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GD82559ER — Networking Silicon Symbol 6.1.2.2 100BASE-TX Scrambler and MLT-3 Encoder Data is scrambled in 100BASE-TX to reduce electromagnetic emissions during long transmissions of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B encoder block and presents ...
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Clock NRZ NRZ1 MLT-3 6.1.2.3 100BASE-TX Transmit Framing The PHY unit does not differentiate between the fields of the MAC frame containing preamble, Start of Frame Delimiter, data and Cyclic Redundancy Check (CRC). The PHY unit encodes the first byte ...
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GD82559ER — Networking Silicon 6.1.3 100BASE-TX Receive Blocks The receive subsection of the PHY unit accepts 100BASE-TX MLT-3 data on the receive differential pair. Due to the advanced digital signal processing design techniques employed, the PHY unit will accurately receive ...
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Collision Detection 100BASE-TX collisions in half duplex mode only are detected similarly to 10BASE-T collision detection, via simultaneous transmission and reception. 6.1.5 100BASE-TX Link Integrity and Auto-Negotiation Solution The 82559 Auto-Negotiation function automatically configures the device to the ...
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GD82559ER — Networking Silicon 6.2.2 10BASE-T Transmit Blocks 6.2.2.1 10BASE-T Manchester Encoder After the 2.5 MHz clocked data is serialized Mbps serial stream, the 20 MHz clock performs the Manchester encoding. The Manchester code always has a ...
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All other activity is determined to be either data, link test pulses, Auto-Negotiation fast link pulses, or the idle condition. When activity is detected, the carrier sense signal is asserted to the MAC. 6.2.3.3 10BASE-T Error Detection and Reporting In ...
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GD82559ER — Networking Silicon 6.3.1 Description Auto-Negotiation selects the fastest operating mode (in other words, the highest common denominator) available to hardware at both ends of the cable. A PHY’s capability is encoded by bursts of link pulses called Fast ...
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Auto-Negotiation or Parallel Detection with no data packets being transmitted. Connection is then established either by FLP exchange or Parallel Detection. The PHY unit will look for both FLPs and link integrity pulses. The following diagram illustrates this ...
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GD82559ER — Networking Silicon 82559ER SpeedLED 46 LILED LILED Figure 16. Two and Three LED Schematic Diagram ...
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PCI Configuration Registers The 82559ER acts as both a master and a slave on the PCI bus master, the 82559ER interacts with the system main memory to access data for transmission or deposit received data ...
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GD82559ER — Networking Silicon 7.1.2 PCI Command Register The 82559ER Command register at word address 04h in the PCI configuration space provides control over the 82559ER’s ability to generate and respond to PCI cycles register, the 82559ER is logically disconnected ...
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PCI Status Register The 82559ER Status register is used to record status information for PCI bus related events. The format of this register is shown in the figure below. Detected Parity Error Signaled System Error Received Master Abort Received ...
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GD82559ER — Networking Silicon Bits Name 24 Parity Error Detected 23 Fast Back-to-Back 20 Capabilities List 19:16 Reserved 7.1.4 PCI Revision ID Register The Revision 8-bit read only register with a default value of 08h for the ...
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Note: Bit 3 is set to 1b only if the value 00001000b (8H) is written to this register, and bit 4 is set to 1b only if the value of 00010000b (16H) is written to this register. All other bits ...
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GD82559ER — Networking Silicon 31 Reserved I/O space indicator Note: Bit 0 in all base registers is read only and used to determine whether the register maps into memory or I/O space. Base registers that map to memory space must ...
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PCI Subsystem Vendor ID and Subsystem ID Registers The Subsystem Vendor ID field identifies the vendor of an 82559ER-based solution. The Subsystem Vendor ID values are based upon the vendor’s PCI Vendor ID and is controlled by the PCI ...
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GD82559ER — Networking Silicon 7.1.13 Interrupt Pin Register The Interrupt Pin register is read only and defines which of the four PCI interrupt request pins, INTA# through INTD#, a PCI device is connected to. The 82559ER is connected the INTA# ...
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Bits Default 24:22 000b (PCI 18:16 010b 7.1.19 Power Management Control/Status Register (PMCSR) The Power Management Control/Status is a word register used to determine and change the current power state of the ...
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GD82559ER — Networking Silicon 7.1.20 Data Register The data register is an 8-bit read only register that provides a mechanism for the 82559ER to report state dependent maximum power consumption and heat dissipation. The value reported in this register depends ...
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Control/Status Registers 8.1 LAN (Ethernet) Control/Status Registers The 82559ER’s Control/Status Register (CSR) is illustrated in the figure below. D31 Upper Word SCB Command Word EEPROM Control Register PMDR Reserved NOTE: In Figure 23 above, SCB is defined as the ...
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GD82559ER — Networking Silicon MDI Control Register: Receive DMA Byte Count: Flow Control Register: PMDR: General Control: General Status: 8.1.1 System Control Block Status Word The System Control Block (SCB) Status Word contains status information relating to the 82559ER’s Command ...
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System Control Block Command Word Commands for the 82559ER’s Command and Receive units are placed in this register by the CPU. Bits Name Specific 31:26 Interrupt Mask 23:20 CUC 19 Reserved 18:16 RUC 8.1.3 System ...
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GD82559ER — Networking Silicon Bits Interrupt Enable. When this bit is set software, the 82559ER asserts an interrupt to 29 indicate the end of an MDI cycle. Ready. This bit is set the 82559ER ...
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Bits Default 29 0b 28:26 000b Note: The PMDR is initialized at ALTRST# reset only. 8.1.12 General Control Register The General Control register is a byte register and is described below. Bits Default 7:2 000000b 1 ...
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GD82559ER — Networking Silicon 8.2 Statistical Counters The 82559ER provides information for network management statistics by providing on-chip statistical counters that count a variety of events associated with both transmit and receive. The counters are updated by the 82559ER when ...
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ID 48 Receive Resource Errors 52 Receive Overrun Errors 56 Receive Collision Detect (CDT) 60 Receive Short Frame Errors 64 Flow Control Transmit Pause 68 Flow Control Receive Pause 72 Flow Control Receive Unsupported The Statistical Counters are initially set ...
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GD82559ER — Networking Silicon 64 Datasheet ...
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PHY Unit Registers The 82559ER provides status and accepts management information via the Management Data Interface (MDI) within the CSR space. Acronyms mentioned in the registers are defined as follows self cleared RO - read only E ...
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GD82559ER — Networking Silicon Bit(s) Name 9 Restart Auto- Negotiation 8 Duplex Mode 7 Collision Test 6:0 Reserved 9.1.2 Register 1: Status Register Bit Definitions Bit(s) Name 15 Reserved 14 100BASE-TX Full Duplex 13 100 Mbps Half Duplex 12 10 ...
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Register 2: PHY Identifier Register Bit Definitions Bit(s) Name 15:0 PHY ID (high byte) 9.1.4 Register 3: PHY Identifier Register Bit Definitions Bit(s) Name 15:0 PHY ID (low byte) 9.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions Bit(s) Name ...
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GD82559ER — Networking Silicon 9.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions Bit(s) Name 15:5 Reserved 4 Parallel Detection Fault 3 Link Partner Next page Able 2 Next Page Able 1 Page Received 0 Link Partner Auto- Negotiation Able 9.2 ...
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Bit(s) Name 8 Polarity 7:2 Reserved 1 Speed 0 Duplex Mode 9.3.2 Register 17: PHY Unit Special Control Bit Definitions Bit(s) Name 15 Scrambler By- pass 14 By-pass 4B/5B 13 Force Transmit H- Pattern 12 Force 34 Transmit Pattern 11 ...
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GD82559ER — Networking Silicon Bit(s) Name 0 Jabber Function Disable 9.3.3 Register 18: PHY Address Register Bit(s) Name 15:5 Reserved 4:0 PHY Address 9.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions Bit(s) Name 15:0 Receive False Carrier 9.3.5 ...
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Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit Definitions Bit(s) Name 15:0 Premature End of Frame 9.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions Bit(s) Name 15:0 End of Frame Counter 9.3.10 ...
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GD82559ER — Networking Silicon 72 Datasheet ...
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Electrical and Timing Specifications 10.1 Absolute Maximum Ratings Maximum ratings are listed below: Case Temperature under Bias . . . . . . . . . . . . . . . . . . . . . . ...
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GD82559ER — Networking Silicon V Output High Voltage OHP V Output Low Voltage OLP C Input Pin Capacitance INP C CLK Pin Capacitance CLKP C IDSEL Pin Capacitance IDSEL L Pin Inductance PINP NOTES: 1. These values are only applicable ...
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Input Differential V IDR100 Reject Peak Voltage Input Common Mode V ICM100 Voltage Output Differential V OD100 Peak Voltage Line Driver Supply I CCT100 Peak Current NOTES: Current is measured on all V 1. Transmitter peak current is attained by ...
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GD82559ER — Networking Silicon 10.3 AC Specifications Symbol Parameter Switching Current High I OH(AC) (Test Point) Switching Current Low I OL(AC) (Test Point) Low Clamp I CL Current High Clamp I CH Current PCI Output Rise slew RP Slew Rate ...
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Timing Specifications 10.4.1 Clocks Specifications 10.4.1.1 PCI Clock Specifications The 82559ER uses the PCI Clock signal directly. measurement points for the PCI Clock signal. 0.475V 0.4V CC 0.325V CC Symbol T1 T cyc T2 T high T3 T low ...
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GD82559ER — Networking Silicon 10.4.2 Timing Parameters 10.4.2.1 Measurement and Test Conditions Figure 27, Figure 28, and done. The component test guarantees that all timings are met with minimum clock slew rate (slowest edge) and voltage swing. The design must ...
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NOTE: Input test is done with 0.1V for testing input timing. 10.4.2.2 PCI Timings Symbol T14 t val T15 t val(ptp) T16 t on T17 t off T18 t su T19 t su(ptp) T20 t h T21 t rst T22 ...
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GD82559ER — Networking Silicon Symbol T35 t flrwc T36 t flacc T37 t flce T38 t floe T39 t fldf T40 t flas T41 t flah T42 t flcs T43 t flch T44 t flds T45 t fldh T46 t ...
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EEPROM Interface Timings The 82559ER is designed to support a standard 64x16, or 256x16 serial ...
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GD82559ER — Networking Silicon 10.4.2.5 PHY Timings Symbol T56 T nlp_wid T57 T nlp_per Normal Link Pulse Symbol ...
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Fast Link Pulse FLP Bursts Symbol T64 T jit Datasheet Networking Silicon — GD82559ER T59 T60 T58 Clock Pulse Data Pulse T63 T62 Figure 32. Auto-Negotiation FLP Timings Table 30. 100Base-TX Transmitter AC Specification Parameter Condition TDP/TDN Differential HLS Data ...
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GD82559ER — Networking Silicon 84 Datasheet ...
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... The GD82559ER is a 196-pin Ball Grid Array (BGA) package. Package dimensions are shown in Figure 24. More information on Intel device packaging is available in the Intel Packaging Handbook, which is available from the Intel Literature Center or your local Intel sales office. Datasheet Figure 24. Dimension Diagram for the GD82559ER 196-Pin BGA Networking Silicon — ...
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GD82559ER — Networking Silicon 12.2 Pinout Information 12.2.1 GD82559ER Pin Assignments Pin A10 A13 B10 B13 C10 C13 D10 D13 E10 E13 ...
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Pin H10 H13 J10 J13 K10 K13 L10 L13 M10 FLA15/EESK M13 N10 FLA14/EEDO N13 P10 FLA13/EEDI P13 Datasheet ...
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GD82559ER — Networking Silicon 12.2.2 GD82559ER Ball Grid Array Diagram ...