TXC-06885BIOG Transwitch Corporation, TXC-06885BIOG Datasheet - Page 103

• Manufacturer Part Number: TXC-06885BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06885BIOG

• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temperature Classification: Industrial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

27B4
27B8
27BC RW
27C0
27C4
PRELIMINARY TXC-06885-MB, Ed. 6A
February 2005
(hex)
Addr
RW
RO
RW
RO
RW
RW
Mode
15-0
31-16
15-0
31-16
31-0
31-0
31-0
range
Bit
value after
FFFF
0
FFFF
0
FFFFFFFF Ingress FIFO Full Interrupt Mask Per Port: FIFO full interrupt mask for
FFFFFFFF Ingress FIFO Near Full Interrupt Mask Per Port: FIFO Near full
FFFFFFFF Ingress FIFO PHY/Port Enable Per Port: Ingress FIFO/Port Enable
Default
reset
- Memory Maps and Bit Descriptions -
Pause Frame Regeneration Timer CMAC C: This register sets the
Pause frame regeneration time in Pause Quanta (1 Pause Quanta = 512
bit times) for ports 16 to 23, (serviced by Configurable MAC C). The
Pause Frame Regeneration time sets the time between consecutive
Pause frames from an ethernet port, while the port is in the Pause
Generation state.
Note: Pause frame generation state is reached once the Pause high
threshold is crossed and the Pause low threshold is not reached.
Reserved
Pause Frame Regeneration Timer CMAC D: This register sets the
Pause frame regeneration time in Pause Quanta (1 Pause Quanta = 512
bit times) for ports 24 to 31, (serviced by Configurable MAC D). The
Pause Frame Regeneration time sets the time between consecutive
Pause frames from an ethernet port, while the port is in the Pause
Generation state.
Note: Pause frame generation state is reached once the Pause high
threshold is crossed and the Pause low threshold is not reached.
Reserved
the 32 Ingress FIFOs (one per port). When 0, disables the mask and an
interrupt will be generated when the appropriate FIFO becomes full. The
interrupt is cleared by reading the status register Ingress FIFO Full
Status. If this bit is 1, no interrupt will be generated.
interrupt mask for the 32 Ingress FIFOs (one per port). When 0, disables
the mask and an interrupt will be generated when the appropriate FIFO
becomes Near full. The interrupt is cleared by reading the status register
Ingress FIFO Near Full Status. If this bit is 1, no interrupt will be
generated. A Port will go into a near full condition when its Ingress FIFO
level goes beyond the Pause Frame High Threshold value associated
with the port.
bits for the 32 Ingress FIFOs (one per port).
Description
Envoy-CE4 Device
DATA SHEET
TXC-06885
1 03 o f 12 8