SRCS14L Intel (CPU), SRCS14L Datasheet - Page 9

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SRCS14L

Manufacturer Part Number
SRCS14L
Description
Manufacturer
Intel (CPU)
Datasheet

Specifications of SRCS14L

Lead Free Status / RoHS Status
Supplier Unconfirmed
2.2.1.1
2.2.1.2
2.2.1.3
2.2.2
2.2.3
2.2.4
2.2.5
Technical Product Specification
SATA Controllers
Processor Core
The 80303 uses the 80960JT-100 core. The core processor runs at 100 MHz with an internal 64-bit
100 MHz PCI bus. Among other features, it contains a 128-bit register bus, 16Kbyte two-way
instruction cache, 4Kbyte direct-mapped data cache, 1Kbyte zero wait state data RAM, and single
clock execution of most instructions.
PCI-to-PCI Bridge
The PCI-to-PCI bridge features fully independent PCI bus operation with independent clocks,
dedicated data queues, 32-bit/33Mhz and 64-bit/66Mhz PCI bus support, and 64-bit Dual Address
Cycle addressing.
Memory Controller Unit
The Memory Controller provides direct control of memory systems external to the 80960 core
processor, including SDRAM and Flash. It features programmable chip selects, a wait state
generator, ECC single-bit correction and double-bit error detection. The bus interface to the
memory controller operates at 100 MHz. The SRCS14L uses 64MB of embedded memory.
Intel
This 3.3v, 32Mb (4MB) flash memory chip is used to store the RAID firmware. This non-volatile
storage can be accessed for firmware updates and recovery. For firmware recovery, set the IOP
mode select jumper J1 to reset; place jumper on pins 1 and 2. For normal firmware updates, place
the jumper on pins 2 and 3 (or remove totally). See
more information.
SDRAM (Cache)
The SRCS14L provides 64MB of 3.3v PC-100 ECC unbuffered CAS 2 latency SDRAM. The
memory is embedded in the RAID controller and is not upgradeable. It is connected directly to the
memory controller interface bus of the IOP, and serves as storage for the executable code
transferred from the flash. It also serves as cache during RAID transactions. Cache mode selection
takes immediate effect while the server is online. The IOP memory controller provides single-bit
ECC error correction.
The SRCS14L has two Silicon Image Sil3112A SATA controllers, which each control two serial
ports (four ports total). The Sil3112A can support data transfer rates up to 1.5 Gbps. See http://
www.siliconimage.com/products/sii3112.asp for more information.
Audible Alarm
An 80db audible alarm is mounted on the RAID controller to alert the user to a number of software
and/or hardware events experienced by the controller.
®
Smart 3 FlashFile™ Flash Memory
Intel® Integrated RAID Controller SRCS14L
Figure 2: Jumper Settings and Pin Numbers
for
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