82V2082PF IDT, Integrated Device Technology Inc, 82V2082PF Datasheet - Page 30

• Manufacturer Part Number: 82V2082PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2082PF

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.5
uator can be deployed in the transmit path or the receive path, and can also
be disabled. This is selected by the JACF[1:0] bits (JACF, 03H...).
depth of FIFO can be selected by JA[1:0] pins on a global basis. Refer to
HARDWARE CONTROL PIN SUMMARY
3.5.1
Figure-13. The FIFO is used as a pool to buffer the jittered input data, then
the data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the JADP[1:0] bits
(JACF, 03H...). In hardware
by JA[1:0] pins on a global basis. Refer to
MARY
will be 16 bits, 32 bits or 64 bits. Deeper FIFO can tolerate larger jitter, but
at the cost of increasing data latency time.
FUNCTIONAL DESCRIPTION
IDT82V2082
There is one Jitter Attenuator in each channel of the LIU. The Jitter Atten-
In hardware
The Jitter Attenuator is composed of a FIFO and a DPLL, as shown in
Jittered Clock
Jittered Data
for details. Consequently, the constant delay of the Jitter Attenuator
JITTER ATTENUATOR
JITTER ATTENUATION FUNCTION DESCRIPTION
control
Figure-13 Jitter Attenuator
W
mode, Jitter Attenuator position, bandwidth and the
32/64/128
control
FIFO
DPLL
MCLK
mode, the depth of FIFO can be selected
for details.
5 HARDWARE CONTROL PIN SUM-
R
De-jittered Data
De-jittered Clock
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
RDn/RDPn
RDNn
RCLKn
5
30
6.8 Hz, as selected by the JABW bit (JACF, 03H...). In T1/J1 applications,
the Corner Frequency of the DPLL can be 1.25 Hz or 5.00 Hz, as selected
by the JABW bit (JACF, 03H...). The lower the Corner Frequency is, the
longer time is needed to achieve synchronization.
will overflow. This overflow is captured by the JAOV_IS bit (INTS1, 19H...).
If the incoming data moves slower than the outgoing data, the FIFO will
underflow. This underflow is captured by the
For some applications that are sensitive to data corruption, the JA limit
mode can be enabled by setting JA_LIMIT bit (JACF, 03H...) to ‘1’. In the
JA limit mode, the speed of the outgoing data will be adjusted automatically
when the FIFO is close to its full or emptiness. The criteria of starting speed
adjustment are shown in Table-16. The JA limit mode can reduce the pos-
sibility of FIFO overflow and underflow, but the quality of jitter attenuation
is deteriorated.
Table-16 Criteria of Starting Speed Adjustment
3.5.2
ITU-T I.431, G.703, G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/
13, AT&T TR62411 specifications. Details of the Jitter Attenuator perfor-
mance is shown in
Characteristics.
In E1 applications, the Corner Frequency of the DPLL can be 0.9 Hz or
When the incoming data moves faster than the outgoing data, the FIFO
The performance of the Jitter Attenuator in the IDT82V2082 meets the
FIFO Depth
32 Bits
JITTER ATTENUATOR PERFORMANCE
Table-68 Jitter Tolerance
Criteria for Adjusting Data Outgoing Speed
2 bits close to its full or emptiness
3 bits close to its full or emptiness
4 bits close to its full or emptiness
and
JAUD_IS
Table-69 Jitter Attenuator
bit (INTS1, 19H...).
May 4, 2009