TXC-03401BITQ Transwitch Corporation, TXC-03401BITQ Datasheet - Page 5

• Manufacturer Part Number: TXC-03401BITQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03401BITQ

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Proprietary TranSwitch Corporation Information for use Solely by its Customers
DS3F
DATA SHEET
TXC-03401B
mode, the C-bits may be generated internally (such as C-bit parity), written by the microprocessor (such as the
FEAC channel), or provided from the external C-bit interface. In C-bit Parity mode, the C1 bit is always trans-
mitted as a 1. The transmit C-bit interface consists of a data input signal (CXD), a clock signal (CXCK), a fram-
ing pulse (CXF) and a data communication link clock (CXDCC). For M13 mode, all of the C-bits are input from
the terminal side’s bit-serial interface. The DS3 transmit line side interface consists of the data signal (D3TD)
and a clock signal (D3TC).
DS3F transmit-to-receive (TR) loopback is controlled by setting a bit in the memory map (3LOOP). The entire
device is used when loopback is in effect, but the line side input data and clock are blocked (by the gate pre-
ceding the DS3 Frame Alignment Block shown in Figure 1). In the Extended-features mode of operation, a
receive-to-transmit payload (RTP) loopback is also available by use of control bit RTPLOOP .
The capability to generate and transmit single overhead bit errors is also provided. External interfaces are pro-
vided for transmitting a far end block error (FORCEFEBE), a P-bit parity error (FORCEPP), a C-bit parity error
(FORCECP) and an overhead bit error (FORCEOE). The FORCEOE signal is used in conjunction with the
enable signal (OENA) for introducing an overhead bit error in the next 85-bit segment of the DS3 frame. When
the Extended-features mode (EMODE), Coding Violation Enable (CVEN) and Excessive Zeros Enable
(EXZEN) control bits in the memory map are set to 1, the Coding Violations Count (CVCNT) function and
Excessive Zeros Count (EXZCNT) functions pin replace the FORCECP and FORCEPP functions, respectively.
The purpose of these pins is to utilize the DS3F's 16-bit counter CVEXZ to count coding violation and/or exces-
sive zeros events. Indications of these events are provided to the DS3F by TranSwitch's ART or ARTE devices
(TXC-02020/02021). The ART's CV output pin indicates both coding violations and excessive zeros. Therefore,
only the CVCNT input pin to the DS3F is required to count both types of event. When the ARTE is used in con-
junction with the DS3F, there are separate CV and EXZ inputs available to the DS3F, which can be or-gated
together in the DS3F's 16-bit counter, if required. The DS3F has an internal 16-bit shadow counter incorpo-
rated into its counter design. This prevents CV or EXZ counts being lost during a read cycle.
The Transmit Frame Reference Generator Block provides reference timing for bit-serial operation. This block
accepts an external 44.736MHz clock signal (TCIN) and derives a clock signal (TCOUT), a framing pulse
(TFOUT), a clock gap signal (TCG) and a data signal (TDOUT). The DS3 data signal consists of framing bits
and zeros elsewhere. An optional input framing pulse (TFIN) is also provided, but is not required for normal
operation.
The DS3F microprocessor bus interface consists of eight bidirectional data and address pins (AD0-AD7),
along with other microprocessor control pins. The microprocessor bus is used to write control information and
to read status information and alarms. When operating in the Extended-features mode the DS3F memory map
contains twenty-one effective addresses (00H-14H), compared with eight (00H-07H) in the Normal mode.
When the DS3F is operating in the Extended-features mode, its many additional features may be activated via
control bits in the memory map. These features include: ability to tri-state all output ports, X-bit inversion,
receive loop timing, receive and transmit Blue Code AIS conditions, FEAC Idle Channel Indication, a receive
FEAC FIFO stack overflow bit, a Severely Errored Frame indication, and double FEAC word handling.
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TXC-03401B-MB
Ed. 6, June 2001