TXC-03401BITQ Transwitch Corporation, TXC-03401BITQ Datasheet - Page 40

• Manufacturer Part Number: TXC-03401BITQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03401BITQ

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Address
0A
0B
0C
09
4-1
7-0
7-0
Bit
7
6
5
0
7
6
5
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TESTLOCK Test Lock: Test bit to reset the transmit frame counter at a different time
RTPLOOP
STKOVFL
RTPLLEN
Symbol
Unused
Unused
RBLUE
SEF
Severely Errored Frame Indication: A 1 indicates that a Severely Errored
Frame condition (SEF) has been detected. An SEF is defined as 3 out of
16 F-bits in error, utilizing a sliding window of 16 bits. This is a latched bit,
and it clears on a microprocessor read cycle. This bit will then relatch if the
condition that causes this bit to latch is still present.
This bit is internally set to 0.
Receive Blue code AIS condition: When this bit is set to 1, the device
has detected all 1’s. This is a latched bit, and it clears on a microprocessor
read cycle. This bit will then relatch if the condition that causes this bit to
latch is still present.
These four bits are internally set to 0.
Stack Overflow indicator for register OFH receive FEAC FIFO: This bit
is set to 1 when the receive FEAC circuit has detected and stored in its
stack more than four FEAC words since the last read of register OFH. This
is a latched bit, and it clears on a microprocessor read cycle.
Counter for errored DS3 F-bits (and M-bits): An 8-bit saturating counter
that counts the number of F-bits that are in error since the last read cycle, if
FBEC at Address 08H, bit 7 is set to 1. If FBEC is set to 0, this counter will
count both F-bit and M-bit errors. The counter is cleared on a microproces-
sor read cycle.
Counter for errored DS3 M-bits (and F-bits): An 8-bit saturating counter
that counts the number of M-bits that are in error since the last read cycle,
if MBEC at Address 08H, bit 6 is set to 0. If MBEC is set to 1, this counter
will count both M-bit and F-bit errors. The counter is cleared on a micropro-
cessor read cycle.
Receive-to-Transmit Payload Loopback Lock Enable: To activate
receive-to-transmit payload loopback, this bit must first be set to 1 for at
least one frame after RTPLOOP (bit 6) has been set to 1 and then be set to
0. This resets the transmit frame counter so that the data will be synchro-
nized to the overhead bits when using the loopback. The loopback com-
mences on the transition to 0 and terminates when RTPLOOP is cleared to
0.
Receive-to-Transmit Payload Loopback: This bit must be set to 1 to per-
mit RTPLLEN (bit 7) to activate receive-to-transmit payload loopback. This
loopback causes the receive output data (payload only) to be internally
connected to the transmit side data input, as shown in Figure 1. The loop-
back condition is terminated by clearing this bit to 0. The XFSI input pulse
must not be applied while RTPLOOP is set to 1.
with respect to the receive. For test purposes only. Normally set to 0.
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DATA SHEET
Description
TXC-03401B
TXC-03401B-MB
Ed. 6, June 2001
DS3F