HFIXF1110CC Intel, HFIXF1110CC Datasheet - Page 86

• Manufacturer Part Number: HFIXF1110CC
• Manufacturer: Intel

Specifications of HFIXF1110CC

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
5.5.6
5.5.6.1
07-Oct-2005
86
®
Figure 22. Mode 1 Timing
Table 25. Mode 1 Clock Cycle to Data Bit Relationship
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Note:
When this operation mode is implemented on a board with a shift register chain containing three
74HC595 devices, the LED DATA bit 1 is output on Shift Register bit 1, and so on up the chain.
Only Shift Register bits 31 and 32 do not contain valid data. The actual data shown in
consists of a 36-bit chain, of which 30 bits are valid LED DATA. The 36-bit data chain is built up
as follows:
The LED_DATA signal is now inverted from the state in Mode 0.
Power-On, Reset, and Initialization
The LED interface is disabled at power-on or reset. The system software controller must enable the
LED interface. The internal state machines and output pins are held in reset until the full IXF1110
MAC configuration is completed.
Enabling the LED Interface
“LED Control ($
by setting the LED_ENABLE bit to a logic 1. The power-on default for this bit is Logic 0.
“Port Enable ($
be enabled for the LEDs to operate for that port. If the port is not enabled, the LEDs will be off for
that port. The power-on default for this register is 0x3FF, which means all ports are enabled.
“Link LED Enable ($
by the system software. This enables the per-port link LEDs for the IXF1110 MAC. Link LEDs do
not automatically update. For more details on which LEDs are affected by this register, refer to
section
LED_CLK
CYCLE
34:36
4:33
LED_LATCH
2:3
LED_DATA
1
LED_CLK
Section 5.5.7.1, “LED Signaling Behavior” on page
Intel
START BIT
PAD BITS
LED DATA 1-30
PAD BITS
LED_DATA
®
NAME
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
0x500)”: This register enables and disables ports on a per port basis. A port must
0x509)”: This register must be set to globally enable LED interface. This is done
1
0x502)”: This register must be set on a per port basis when link is detected
Order Number: 250210, Revision: 009
2
This bit has no meaning in Mode 1 operation and is shifted out of the 32-stage shift
register chain before the LED_LATCH signal is asserted.
These bits have no meaning in Mode 1 operation and are shifted out of the 32-stage
shift register chain before the LED_LATCH signal is asserted.
These bits are the actual data to be transmitted to the 32-stage shift register chain. The
decode for each bit in each mode is defined in
The data is INVERTED. Logic 1 (LED ON) = Low.
These bits have no meaning in Mode 1 operation and are latched into positions 31 and
32 in the shift register chain. These bits are not considered as valid data and should be
ignored. They should always be a Logic 0 = High.
3
1
4
26
23 24 25 26 27 28 29 30
27
28
LED_DATA DESCRIPTION
29
30
87.
31
Table 25 on page
32
33
34
86.
35
36
Figure 22
Datasheet