HFIXF1110CC Intel, HFIXF1110CC Datasheet - Page 168

• Manufacturer Part Number: HFIXF1110CC
• Manufacturer: Intel

Specifications of HFIXF1110CC

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
07-Oct-2005
168
®
Table 96. TX FIFO MAC Transfer Threshold Ports 0 to 9 ($ 0x614 - 0x61D) (Sheet 3 of 3)
Table 97. TX FIFO Overflow Event ($ 0x61E) (Sheet 1 of 2)
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
TX FIFO MAC
Transfer
Threshold Port 7
TX FIFO MAC
Transfer
Threshold Port 8
TX FIFO MAC
Transfer
Threshold Port 9
Register Description: This register provides status that a FIFO- full situation has occurred (for
example, a FIFO overflow). The bit position equals the port number.
This register is cleared on Read.
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. For all MAC Transfer Threshold Registers, the following bit definitions apply to all ports (0:9):
3. For proper operation of the IXF1110, the MAC transfer threshold must be set to greater than the MaxBurst1
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
31:10
Bits 31:13 - Reserved and R.
Bits 12:0 - Described above.
on the SPI4-2.
Bit
9
8
Name
2
Intel
TX FIFO Overflow
TX FIFO Overflow
Event Port 9
Event Port 8
®
Reserved
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Name
Description
Sets the value at which the FIFO begins to
transfer data to MAC. The bottom 3 bits of this
register are ignored, thus the threshold is set in
increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
Sets the value at which the FIFO begins to
transfer data to the MAC. The bottom 3 bits of
this register are ignored, thus the threshold is
set in increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
Sets the value at which the FIFO begins to
transfer data to the MAC. The bottom 3 bits of
this register are ignored, thus the threshold is
set in increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
Order Number: 250210, Revision: 009
3
Reserved
Port 9
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred
Port 8
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred
Description
Address
0x61B
0x61C
0x61D
Type
CoR
CoR
R
Type
R/W
R/W
R/W
1
1
0x00000000
0x00000100
0x00000100
0x00000100
0x000000
Default
Default
Datasheet
0
0